BENDIXKing KY 96A, Maintenance Manual

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B
KY 96A, KY 97A
Rev 5, Apr 2003 MM 006-05674-0005.dwd Page 4-9
The microprocessor (uP), pin 32, sends two 24 bit serial data streams to the synthe-
sizer PLL IC (I103) on the main board. Only the last 20 bits are used by the synthe-
sizer PLL IC. The first stream provides the crystal divide ration and the second pro-
vides the frequency to be divided. Each data bit is clocked from pin 33 of the uP. At
the end of each data stream, a high going strobe pulse is sent from pin 28 of the uP to
latch the last 20 bits of data into the synthesizer PLL IC.
When the synthesizer is locked, pin 25 (Lock Detect) of uP is pulled high from the syn-
thesizer PLL IC I103. If pin 29 (Mic key(not)) of uP is low, pin 22 (TX) of the uP is taken
high to turn on the transmitter when synthesizer is in lock. The gate of Q701 must be
pulled low for the uP to take TX high. Then TX is inverted through Q707 to turn on the
transmitter.
4.3.5.2 Communication to Non-Volatile Memory
When the non-volatile memory (I704) is being addressed, pin 24 of the uP is high.
When reading from the memory, a 16 bit serial code/ address stream is sent out on pin
32 of the uP, then a serial 16 bit data stream associated with the address is read back
on pin 31 of the uP. When writing to the memory, a 16 bit serial code/ address stream
followed by a 16 bit serial data stream associated with the address, are sent out of pin
32 of the uP. Only the last 9 bits of the 16 bit code/ address stream are used by the
non-volatile memory. Each bit of the code/ address and data streams is clocked from
pin 33 of the uP.
4.3.5.3 Communication to Analog to Digital Converter
When the analog to digital converter (A/D) (I706) is addressed, pin 23 of the uP is low.
A serial 8 bit address stream is sent to the A/D from pin 32 of the uP requesting con-
version data. Simutaneously, a serial 8 bit data stream of the last requested conver-
sion data is received from the A/D on pin 31 of the uP. This makes communication
full duplex. Only the first 4 bits of the address stream are used by the A/D. Each bit
of the address and conversion data streams is clocked from pin 33 of the uP.
The A/D uses a system clock for its conversion time. The 496.875 kHz system clock
is generated from I705, a binary counter. The 3.975 MHz clock signal (synthesizer
PLL IC) on pin 1 of I705 is divided by 8, then output on pin 9 of I705.
4.3.5.4 Microprocessor Reset Circuit
During normal operation the output on pin 13 of I701A is 5 volts DC. The 5 volts DC
on pin 40 (Vdd) of the uP, is produced through the 5 volt regulator I108 on the main
board. On power up, the 9 volts on the input of I108 must reach 7.3 volts DC before
5 volts DC is produced on the output of I108. Therefore, on power up the uP (pin 1) is
held in reset until the 9 volt DC reaches 7.9 volts DC. Pin 11 of I701A must reach 6.2
volts DC to accomplish this. On power down, the 9 volt DC must drop to 7.5 volts DC
before the uP is put into reset.
4.3.5.5 Display