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4. BIOS Setup
4.5.1 Auto Configuration
This item allows you to select pre-determined optimal values for DRAM, cache and timing
according to CPU type & system clock. The choice: Enabled, Disabled.
Note:
When this item is enabled, the pre-defined items will become SHOW-ONLY
4.5.2 RAS Pulse Width Refresh
Leave on default setting.
4.5.3 RAS Precharge Time
This controls the idle clocks after issuing a precharge command to SDRAM. Leave on
default setting, which is controlled by SPD.
4.5.4 RAS to CAS Delay
This controls the latency between SDRAM active command and the read/write command.
Leave on default setting, which is controlled by SPD.
4.5.5 Concurrent function(MEM)
If each bus master cycle does not take the same path, it allows the multiple bus master
cycles to be acted at the same time.
4.5.6 Concurrent function(PCI)
If each bus master cycle does not take the same path, it allows the multiple bus master
cycles to be acted at the same time.
4.5.7 CPU Pipeline Control
Enable/disable the CPU pipeline control. The choice: Enabled, Disabled.
4.5.8 Starting Point of Paging
This value controls the start timing of memory paging operations. The choice: 1T, 2T, 4T,
8T.
4.5.9 SDRAM WR Retire Rate
The system designer must select the correct timing for data transfers from the write buffer to
memory, according to DRAM specifications. The choice: X-1-1-1, X-2-2-2.
4.5.10 CPU to PCI Burst Mem. WR
Select enabled permits PCI burst memory write cycles, for faster performance. When
