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Page 4 of 4 - 22 March 2005 

Technical specifications are subject to change without prior notice          

 

 

 

 

Barco Silex overview 

 

Barco Silex is a micro-electronic design house located in Belgium and France belonging to the Belgian 

Barco group. 

 
Barco Silex offers a complete portfolio of high-end design services, from ASIC/FPGA design to advanced 

SoC/SoPC based system development, IP-core design and board design in the fields of: 

 

 

image processing  

 

communications 

 

consumer electronics 

 

industrial electronics. 

 

Barco Silex IP products 

 
Barco Silex design expertise is also made available through a wide portfolio of IP products, with a strong 

focus on high performance, standardized image processing and encryption functions. 

All these IP cores have been designed and fully validated by Barco Silex and are hardware proven, 

which guarantees high IP quality as well as best support during your integration phase.   
 

Deliverables include: 

 

RTL Code or netlist (depending on license type) 

 

Functional simulation testbench 

 

Synthesis script 

 

Full documentation 

For some of them, we can also provide you with simulation models and a design kit. 

 

These "off the shelf", high quality IP cores provide you with the fastest and most efficient way of 

integrating complex functionalities on FPGAs or ASICs, while meeting short time to market constraints. 
 

More information 

 

Order-reference: BA132MPEG4D 
 

For additional information and other IP products contact: 

Barco – Silex 
e-mail: 

[email protected]

 

http://www.barcodesignservices.com

 

 

or the local Barco Silex design centers: 

 

 

Belgium 

France 

 

Scientific Park 

ZI Peynier- Rousset 

 

 

Rue du Bosquet 7 

Route de Trets Imm CCE 

 

1348 Louvain-la Neuve  13790 Peynier 

 +32(0)10/45.49.04  +33(0)44/216.41.06

 

 

Summary of Contents for BA132

Page 1: ...ted AC DC coefficient prediction Easy synchronous pixel and stream interfaces Off chip reference frame store with easy memory interface pluggable to any custom memory controller SRAM or SDRAM for instance Minimized off chip data bandwidth Full header decoding data partitioning and short headers not supported Reversible VLC decoding not supported Simultaneous mutliple streams decoding Optional supp...

Page 2: ...ure 1 illustrates a simplified block diagram of the BA132MPEG4D IP showing the internal modules and its interfaces The core accepts the compressed stream at its Compressed Data Interface The stream contains headers The decoded video data is organized in macroblocks under YUV format 4 2 0 resolution One macroblock is made of 4 luminance blocks 8x8 1 Cb block 8x8 and 1 Cr block 8x8 The video data is...

Page 3: ...f Clk Performance MHz Needed Resource3 Troughput Msamples s 1 Altera EP1S25C52 10900 LE s 1 65 90 M4K 30 DSP Multipliers 25 Xilinx XC2V1500 4 5450 Slices 1 65 29 RAMB16 30 MULT18x18 25 1 Results for typical compression as measured on difficult video sequences 2 Estimated contact us for latest figures 3 Resources for single stream decoding contact us for multiple stream implementations Pinout descr...

Page 4: ...d and fully validated by Barco Silex and are hardware proven which guarantees high IP quality as well as best support during your integration phase Deliverables include RTL Code or netlist depending on license type Functional simulation testbench Synthesis script Full documentation For some of them we can also provide you with simulation models and a design kit These off the shelf high quality IP ...

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