Page 3 of 4 - 22 March 2005
Technical specifications are subject to change without prior notice
Texture decoding
This module decodes error frames when dealing with P-VOPs (motion compensated) or complete frames
when dealing with I-VOPs.
The texture decoding works on block level (8x8) and is made of zigzag encoding, inverse quantization,
AC/DC prediction and Inverse Discrete Cosine Transform (IDCT).
Motion compensation
This module is bypassed for Intra-coded pictures (I-VOP). For P-VOPs, it combines the so-called error
picture (coming from the texture decoder) to the reference frame (stored in off-chip memory), using the
movement information carried by the decoded motion vector. The motion compensation unit supports
the definition of a single motion vector per macroblock (the 4MV mode is not supported).
Implementation data
The following table details implementation results of the BA132MPEG4E core on various FPGA
technologies. The core is 100% RTL and ASIC technologies can also be mapped. Performance figures
enable real-time decoding for all Simple Profile L1 to L5 levels.
Device
Logic
3)
# of
Clk
Performance
(MHz)
Needed Resource
3)
Troughput
(Msamples/s)
1)
Altera
EP1S25C5
2)
10900 LE’s
1 65
90 M4K,
30 DSP Multipliers
25
Xilinx
XC2V1500-4
5450
Slices
1 65
29 RAMB16,
30 MULT18x18
25
1) Results for typical compression, as measured on difficult video sequences
2) Estimated (contact us for latest figures)
3) Resources for single-stream decoding (contact us for multiple-stream implementations)
Pinout description
Name
I/O
Size
Comments
Global
CLK I
1
Clock
RESET
I
1
Global asynchronous reset
Command and Control Interface
START
I
1
Start decoding command
DONE
O
1
End of decoding status
ERROR O
1
Error
status
ERRORCODE O
16
Error
code
Compressed Data Interface
CSTRB
I
1
Compressed data strobe
CSTNUM I
3
Compressed
data stream id (0..7)
CD I
8
Compressed
data
CFULL
O
8
Compressed data not ready (1 signal per stream)
Pixel Interface
PFULL
I
1
Pixel not ready
PD O
8
Pixel
data
PSTRB O
1
Pixel
strobe
Memory Interface (read queue)
MRQFULL
I
1
Read request queue full
MRQPUSH
O
1
Push read request
MRQADDR
O
32
Read request address
MRQEMPTY
I
1
Read data queue empty
MRQPOP
O
1
Pop read data
MRQRD
I
32
Read data (16-word burst)
Memory Interface (write queue)
MWQFULL
I
1
Write request queue full
MWQPUSH
O
1
Push write request
MWQADWD
O
32
Write request address and write data (16-word burst)
