The
AZZA
U694 MAINBOARD SERIES
Page 31
SDRAM Cycle Length
Before SDRAM can execute a read command that it receives, there is a delay time, which
is measured in clock cycles (CLK). The lower the delay time the faster the execution of
commands will be. It is therefore desirable to minimize this cycle length. Some memory
modules are unable to deal with short delay times. We recommend that you set this delay
time between 2 and 3 CLK’s (the default is 3). If your system becomes unstable we rec-
ommend that you increase the delay time.
Memory Hole
You can reserve this area of system memory for ISA adapter ROM. When this area is
reserved, it cannot be cached. The user information of peripherals that need to use this
area of system memory usually discusses their memory requirements.
P2C/C2P Concurrency
Sets CPU & PCI transfer as synchronous.
Fast R-W Turn Around
This item controls the DRAM timing. It allows you to enable/ disable the fast read/write
turn around.
System BIOS Cacheable
Selecting “Enabled” allows caching of the system BIOS ROM. This results system
performance. However, if any program writes to this memory area, a system error may
occur.
Video RAM Cacheable
Select Enabled allows caching of the video RAM, resulting in better system performance.
However, if any program writes to this memory area, a system error may occur.
AGP Aperture Size
This field selects the size of the Accelerated Graphics Port (AGP) aperture. The aperture
is a portion of the PCI memory address range dedicated for graphics memory address
space. Host cycles that hit the aperture range are forwarded to the AGP without any
translation. The default is 64MB. You may increase this memory when you need to have
faster access for 3D graphics applications (e.g. games).
AGP-4X Mode
This item allows you to enable / disable the AGP-4X Mode. Before you enable this option
please make sure your AGP card supports the 4X AGP display mode.
Managing The PC BIOS
