The
AZZA
U694 MAINBOARD SERIES
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DRAM Timing By SPD
DRAM Clock
SDRAM Cycle Length
Memory Hole
P2C/C2P Concurrency
Fast R-W Turn Around
System BIOS Cacheable
Video RAM Cacheable
AGP Aperture Size
AGP 4x Mode
AGP Driving Control
AGP Driving Value
AGP Fast Write
OnChip USB
USB Keyboard Support
USB Mouse Support
OnChip Sound
OnChip Modem
CPU to PCI Write Buffer
PCI Dynamic Bursting
PCI Master 0 WS Write
PCI Delay Transaction
PCI #2 Access #1 Retry
AGP Master 1 WS Write
AGP Master 1 WS Read
Memory Parity/ECC Check
:Disabled
:CPU Clk
:3
:Disabled
:Enabled
:Disabled
:Disabled
:Disabled
:64M
:Disabled
:Auto
:DA
:Disabled
:Enabled
:Disabled
:Disabled
:Auto
:Auto
:Enabled
:Enabled
:Enabled
:Enabled
:Enabled
:Enabled
:Disabled
:Disabled
Item Help
Menu Level
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CMOS Setup Utility - Copyright (C) 1984 - 2001 Award Software
Advanced Chipset Features
Managing The PC BIOS
3.5. Advanced Chipset Features
DRAM Timing By SPD
When you select enabled, the system BIOS will read the DRAM parameters from the SPD
chip on the DIMM module and set the DRAM timing automatically.
DRAM Clock
This field allows you to select the DRAM access speed control to the memory perform-
ance. For DRAM clock selection you have the following choices:
CPU CLk
CPU –33M
CPU +33M
