AZZA KT133BL, User Manual

Page: 29 / 47

B
B
B
I
I
I
O
O
O
S
S
S
S
S
S
e
e
e
t
t
t
u
u
u
p
p
p
Note! Using this feature may decrease system performance.
Video BIOS / XXXX-XXXX Shadow
These fields allow you to change the Video BIOS location from ROM to RAM. The system
performance is enhancing when you enable this option, as information access is faster
through RAM than ROM.
3
3
.
.
5
5
A
A
D
D
V
V
A
A
N
N
C
C
E
E
D
D
C
C
H
H
I
I
P
P
S
S
E
E
T
T
F
F
E
E
A
A
T
T
U
U
R
R
E
E
S
S
CMOS Setup Utility - Copyright (C) 1984 - 1999 Award Software
Advanced Chipset Features
DRAM Timing By SPD : Disabled Item Help
DRAM Clock 100MHz
SDRAM Cycle Length 3 Menu Level
Ø
Bank Interleave Disabled
Memory Hole Disabled
PCI Master Pipeline Req Enabled
P2C/C2P Concurrency Enabled
Fast R-W Turn Around Disabled
System BIOS Cacheable Disabled
Video RAM Cacheable Disabled
AGP Aperture Size 64M
AGP 4X Mode Disabled
AGP Driving Control Auto
AGP Driving Value DA
AGP Fast Write Disabled
On Chip USB Enabled
USB Keyboard Support Disabled
OnChip Sound Auto
OnChip Modem Auto
CPU to PCI Write Buffer Enabled
PCI Dynamic Bursting Enabled
PCI Master 0 WS Write Enabled
PCI Delay Transaction Enabled
PCI #2 Access #1 Retry Enabled
AGP Master 1 WS Write Disabled
AGP Master 1 WS Read Disabled
4
4
-
-
9
9
B
B
B
I
I
I
O
O
O
S
S
S
S
S
S
e
e
e
t
t
t
u
u
u
p
p
p
This section allows you to configure the system based on the features of the VIA KT133
chipset. This chipset manages bus speeds and access to system memory resources, such
as DRAM and the external cache. It also coordinates communications between the