32
CMOS Setup Utility—Copyright © 1984—2001 Award Software
Advanced Chipset Features
SDRAM CAS Latency
[3]
Item Help
SDRAM Cycle Time Tras/Trc
[6/8]
Menu Level
SDRAM RAS - to - CAS Delay
[3]
SDRAM RAS Precharge Time
[3]
System BIOS Cacheable
[Disabled]
Video BIOS Cacheable
[Disabled]
Memory Hole At 15M - 16M
[Disabled]
CPU Latency Timer
[Disabled]
Delayed Transaction
[Enabled]
On-Chip Video Window Size
[64MB]
Video BIOS Cacheable
Video BIOS Cacheable
Video BIOS Cacheable
Selecting Enabled allows caching of the video BIOS ROM at C0000h to C7FFFh,
resulting in better video performance.
Memory Hole At 15M
Memory Hole At 15M
Memory Hole At 15M
-
-
-
16M
16M
16M
In order to improve performance, certain space in memory can be reserved for
ISA cards. Such memory must be mapped into the memory space below 16 MB.
CPU Latency Timer
CPU Latency Timer
CPU Latency Timer
This function controls the way in which transfers are carried out on the FSB. This
function must be Enabled to maximize performance.
Delayed Transaction
Delayed Transaction
Delayed Transaction
The chipset has an embedded 32-bit posted write buffer to support delay
transactions cycles. Select Enabled to support compliance with PCI specification
version 2.1.
On
On
On
-
-
-
Chip Video Window Size
Chip Video Window Size
Chip Video Window Size
This mainboard provides DVMT technology feature (Dynamic Video Memory
Technology) to increase the video display performance. There is the AGP VGA
interface on this mainboard to allows the AGP display to use part of the system
BI
OS
BI
OS
BI
OS
BI
OS
BIOS Setup
BIOS Setup
