Axon POS System ONe, Instruction Manual

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DRAM Timing Selectable
When set to “BySPD”, the DRAM timing parameters are set according to DRAM SPD (Serial Presence Detect). When disabled, one can manually set the DRAM
timing parameters through the sub items below. Set to “BySPD” if unsure about this feature.
CAS Latency Time
Controls the latency between the SDRAM Read command and the time data actually becomes available.
DRAM RAS# to CAS# Delay
Controls the latency between the DDR SDRAM active command and the read/write command.
DRAM RAS# Precharge
Controls the idle clocks after issuing a precharge command to the DDRSDRAM.
Precharge Delay (tRAS)
This setting determines the timing delay for DRAM precharge.
System Memory Frequency
Allows user to choose different frequencies of memory module.
System BIOS Cacheable
Selecting “Enabled” allows caching of the system BIOS ROM at F0000h- FFFFFh, resulting in better system performance. However, a system error may occur if
data is written to this area of memory by any programs.
Video BIOS Cacheable
Selecting “Enabled” allows caching of the video BIOS ROM at F0000h-FFFFFh, resulting in better video performance. However, a system error may occur if data
is written to this area of memory by any programs.