AXIOMTEK SBC8440, User Manual, Page: 24 / 86

SBC8440 3.5 Form Factor SBC User’s Manual
Hardware Description
Pin Description Pin Description
23 P14 24 P15
25 P16 26 P17
27 P18 28 P19
29
P20
30
P21
31
P22
32
P23
33
GND
34
GND
35
SHFCLK
36
FLM
37
M
38
LP
39 GND 40 ENABKL
41 GND 42 –SHFCLK
43 VDDM 44 VDDM
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Name Description
P0~P23
Flat panel data output
ENABKL
Activity Indicator and Enable Backlight outputs
SHFCLK
Shift clock. Pixel clock for flat panel data
M
M signal for panel AC drive control
LP Latch pulse. Flat panel equivalent of HSYNC
FLM First line marker. Flat panel equivalent of VSYNC
+12V +12V power from PC power supply
ENAVEE
Power sequencing controls for panel LCD bias volt
–SHFCLK
the inverter signal of SHFCLK
VDDM
3.3V or 5V selected by JP6