SBC82810 Pentium
®
M All-in-One Half-Size Board User’s Manual
Watchdog Timer
64
Watchdog Overview
IRQ/SMI
PCI
Configuration
Registers
Preload Value 1
Preload Value 2
Down-Counter
Reset/Interrupt Control Logic
RESET
The timer uses a 35-bit down-counter. The counter is loaded with the
value from the first Preload register. The timer is then enabled and
starts counting down. The time at which the WDT first starts counting
down is called the first stage. When the host fails to reload the WDT
before the 35-bit down-counter reaches zero, the WDT generates an
internal interrupt. After the interrupt is generated, the WDT loads the
value from the second Preload register into the WDT’s 35-bit down
counter and starts counting down. The WDT is now in the second
stage. When the host still fails to reload the WDT before the second
timeout, the WDT reset the system and sets the timeout bit
(WDT_TIMEOUT). This bit indicates that the System has become
unstable. The process of reloading the WDT involves the following
sequence of writes:
1. Write 80 to offset BAR + 0Ch.
2. Write 86 to offset BAR + 0Ch.
3. Write 1 to WDT_RELOAD in Reload Register.
