AXIOMTEK SBC8168, User Manual

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SBC8168 Socket 370 All-in-One CPU Card Series User’s Manual
Award BIOS Utility 36
z
C8000 - CBFFF Shadow/DC000 - DFFFF Shadow
Shadowing ROM reduces available memory between 640KB and
1024KB. These fields determine whether optional ROM is copied
to RAM or not.
7.5 Advanced Chipset Features
This Setup menu controls the configuration of the motherboard
chipset.
CMOS Setup Utility-Copyright © 1984-2000 Award Software
Advanced Chipset Features
SDRAM CAS Latency Time
3
Item Help
SDRAM Cycle Time Tras/Trc 7/9
SDRAM RAS-to-CAS Delay 3 Menu Level f
SDRAM RAS Precharge Time 3
System BIOS Cacheable Disabled
Video BIOS Cacheable Disabled
Memory Hole at 15M-16M Disabled
CPU Latency Timer Enabled
Delayed Transaction Enabled
AGP Graphics Aperture Size 64MB
Display Cache Frequency 100MHz
System Memory Frequency Auto
On-Chip Video Window Size 64MB
Onboard Display Cache Setting
Initial Display Cache Enabled
CAS# Latency 3
Paging Mode Control Open
RAS-to-CAS Override by CAS# LT
RAS# Timing Fast
RAS# Precharge Timing Fast
ÇÈÆÅ : Move Enter: Select +/-/PU/PD: Value F10: Save ESC: Exit F1: General Help
F5: Previous Values F6: Fail-Safe Defaults F7: Optimized Defaults
z
SDRAM CAS Latency Time
When synchronous DRAM is installed, the number of clock cycles
of CAS latency depends on the DRAM timing. Do not reset this
field from the default value specified by the system designer. The
default setting is
3 .