C M L - 5 4 8 5 U S E R M A N U A L V 1 . 0
0 6 / 2 2 / 0 5
12
BUS_PORT
The BUS PORT provides access to the MCF5485 FLEX Bus data and control signals. Most
signals on the BUS PORT have a peripheral connection on the CML-5485 board. The FBCS0*
chip select is dedicated to the on board flash memory. The board must boot from the on board
flash.
AD30
1 2
AD31
AD28
3 4
AD29
AD26
5 6
AD27
AD24
7 8
AD25
AD22
9 10
AD23
AD20
11 12
AD21
AD18
13 14
AD19
AD16
15 16
AD17
AD14
17 18
AD15
AD12
19 20
AD13
A10
21 22
AD11
AD8
23 24
AD9
AD6
25 26
AD7
AD4
27 28
AD5
AD2
29 30
AD3
AD0
31 32
AD1
RSTO*
33 34
RESET* IN
(Note 1) CLKOUT
35 36
FBCS1*
FBCS2*
37 38
FBCS3*
FBCS4*
39 40
FBCS5*
BWE0*
41 42
BWE1*
BWE2*
43 44
BWE3*
R/W*
45 46
TS*
TA*
47 48
OE*
+3.3V
49 50
GND
Notes:
1) The CLKOUT signal must be enabled by installing option resistor R63. The value of R63 should be selected
to reduce connection reflections of the 50MHz signal.
2) The default bus size of FBCS0* is 16 bits data on AD16 – AD31.
3) The FLEX BUS operates in Multiplexed address and data mode by default. The address port provides de-
multiplexed address signals.