If the delay is negative, the order of the SYNC and OUT pulses is reversed:
The next figure illustrates the relationship between the signals when an external TTL-
level trigger is used:
25
SYNC OUT
(generated by the
internal oscillator)
100 ns, FIXED
OUT1
PW1
(0.25 - 250 us)
DELAY > 0
AMPLITUDE
(0 to 250V)
3V, FIXED
OUT2
PW2 (50 - 200 ns)
AMPLITUDE
(0 to 50V)
SYNC OUT
(generated by the
internal oscillator)
100 ns, FIXED
DELAY < 0
3V, FIXED
OUT1
PW1
(0.25 - 250 us)
AMPLITUDE
(0 to 250V)
OUT2
PW2 (50 - 200 ns)
AMPLITUDE
(0 to 50V)