If the delay is negative, the order of the SYNC and OUT pulses is reversed:
The next figure illustrates the relationship between the signals when an external TTL-
level trigger is used:
20
SYNC OUT
(generated by the
internal oscillator)
50 ns, FIXED
MAIN OUTPUT
PULSE WIDTH
DELAY < 0
AMPLITUDE, VARIABLE
3V, FIXED
+5V (TTL) or -0.8V (ECL)
0V (TTL) or -1.6V (ECL)
LOGIC OUTPUT
+5V (TTL) or -0.8V (ECL)
0V (TTL) or -1.6V (ECL)
LOGIC OUTPUT
Summary of Contents for AV-1030-B
Page 42: ...PERFORMANCE CHECK SHEET 42...
