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9 Clocks
Ultra96-V1 provides the following system clocks to the MPSoC:
-
PS_CLK: PS reference clock 100MHz/3 (
33. 3MHz
), 1.8V LVCMOS
-
GTR_CLK0: USB 3.0 26MHz, LVDS
-
GTR_CLK1: DisplayPort 27MHz, LVDS
These clocks are generated by a Customizable Quad Clock Generator.
10 Reset
Ultra96-V1 Reset is managed by the TI PMIC. At power-up, the ZU3EG is held in reset until all power rails
have ramped up and are stable. A pushbutton allows manually resetting the ZU3EG.
11 Getting Help and Support
If additional support is required, Avnet has many avenues to search depending on your needs.
For general question regarding Ultra96-V1, please visit our website at
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valid.
. Here you can find documentation, technical specifications, videos and
tutorials, reference designs and other support.
Detailed questions regarding Ultra96-V1 hardware design, software application development, using Xilinx
tools, training and other topics can be posted on the Ultra96 Support Forums at
. Avnet’s technical support team monitors the forum during normal
business hours.
Those interested in customer-specific options on Ultra96-V1 can send inquiries to