Avalue Technology ESM-TGH, User Manual

Page: 23 / 88

ESM-TGH User
’s Manual
ESM-TGH User
’s Manual
23
2.3.2.1.5 LPC/eSPI Signals
Signal Signal Description
LPC_FRAME#/
ESPI_CS0#
LPC frame indicates the start of an LPC cycle
ESPI Mode: eSPI Master Chip Select Outputs Driving Chip Select0#. A low
selects a particular eSPI slave for the transaction. Each of the eSPI slaves is
connected to a dedicated Chip Selectn# pin
LPC_AD[0:3]/
ESPI_IO_[0:3]
LPC multiplexed address, command and data bus
ESPI Mode: eSPI Master Data Input / Outputs These are bi-directional
input/output pins used to transfer data between master and slaves.
Multiplexed with LPC_AD[0:3]
LPC_CLK/
ESPI_CK
LPC clock output - 33MHz nominal
ESPI Mode: eSPI Master Clock Output This pin provides the reference timing for
all the serial input and output operations
LPC_SERIRQ/
ESPI_CS1#
LPC serial interrupt
ESPI Mode: eSPI Master Chip Select Outputs Driving Chip Select# A low selects
a particular eSPI slave for the transaction. Each of the eSPI slaves is connected
to a dedicated Chip Selectn# pin
LPC_DRQ0#/
ESPI_ALERT0#
LPC serial DMA request.
ESPI Mode: eSPI pins used by eSPI slave to request service from the eSPI
master.
LPC_DRQ1#/
ESPI_ALERT1#
LPC serial DMA request.
ESPI Mode: eSPI pins used by eSPI slave to request service from the eSPI
master.
2.3.2.1.6 GPIO Signals
Signal Signal Description
GPI[0:4] General purpose input pins.
GPO[0:4] General purpose output pins.
2.3.2.1.7 Power & System Management Signals
Signal Signal Description
SUS_S3# Indicates system is in Suspend to RAM state. Active low output.
BATLOW# Indicates that external battery is low
PWRBTN# Power button to bring system out of S5 (soft off), active on rising edge.