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AV02-4749EN  -  February 9, 2015

Figure 8.  Turn-on & Turn-off Gate waveforms of Q1a & Q1b

As can be seen from Figures 7 and 8, the turn-off speed of the IGBT or SiC/GaN MOSFET will be quite slow, due to the 

capacitive effects of D2 and the gate capacitance of Q1.  To improve the turn-off speed, the board is equipped with diode 

resistor pair footprints at D1 and R5 (not mounted NM) to increase the gate current during turn-off.  The turn-on and 

turn-off speed can be further improved by reducing the gate resistance of R4, however, care must be taken to ensure 

that the gate drive current is not more than 2.5A. 

Figure 8 shows the turn-on signal of IN1+, the turn-on signal at gate of Q1a and the turn-off signal at gate of Q1b.  

Figure 7.  Turn-off & Turn-on Gate waveforms of Q1a & Q1b

Figure 7 shows the turn-off signal of IN1+, the turn-off signal at gate of Q1a and the turn-on signal at gate of Q1b.  

IN1+

Vgs (Q1a)

Vgs (Q1b)

IN1+

Vgs (Q1a)

Vgs (Q1b)

Summary of Contents for ACPL-P349

Page 1: ...negative supply is not needed Note If negative supply is needed S2 S3 jumpers need to be removed 4 Bootstrap Diode D3b and Resistor R6 are connected by default These 2 components are provided to help...

Page 2: ...enerator across IN1 IN1 pins of CON1a to simulate microcontroller output to drive lower arm of the half bridge Inverter b Another 10kHz 5V DC pulse at 180 out of phase to 4a from the dual output signa...

Page 3: ...LEDa LEDa Vcc1a Gnda LEDb LEDb Vcc1b Gndb 0 1 F 0 1 F SS32 SS32 BYM26F 10 F Ta R05P15D R8 1 2 5 6 7 1 2 5 6 7 10 F Ta 10 F Ta TP2b TP3b TP4b TP1b TP2a TP3a TP4a TP1a S1a S2a S1b S2b CON1a CON1b IC1a...

Page 4: ...nts D3b and R6 6 Use a multi channel digital oscilloscope to capture the waveforms at the following points a LED signal at IN1 pin with reference to GND for bottom arm b LED signal at IN2 pin with ref...

Page 5: ...ure 5 accommodates 2 ACPL P349 ACPL W349 IC s Therefore each board is capable of driving top and bottom arms of the half bridge Inverter It allows the designer to test the performance of the gate driv...

Page 6: ...lamping voltage Descriptions of each of the 7 different power supply schemes are provided below Users are encouraged to evaluate all seven schemes to decide which one is most suitable for his her need...

Page 7: ...of negative Vee at Veea Veeb Therefore all S2 s must be open while all S3 s must be shorted Power scheme 7 This scheme is useful if dual output 15V DC DC converters are not available or dual output 9...

Page 8: ...effects of D2 and the gate capacitance of Q1 To improve the turn off speed the board is equipped with diode resistor pair footprints at D1 and R5 not mounted NM to increase the gate current during tur...

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