7
Power scheme 4 - This is another simple scheme offered as an alternative to scheme 1. Here, only 1 external supply is
needed (for Vcc1). Vcc2a is obtained by a lower power DC/DC converter at IC2a with Vcc1 as Vin and +15V output at
Vcc2a with reference to Vea. Vcc2b supply is obtained from Vcc2a by bootstrapping operation. For this to work, the
bootstrap components D3b and R6 must be connected, all S2 jumpers must be shorted so that no negative supply of
Vee is allowed, and the Signal input 2 should be 180
°
out of phase to Signal input 1. S2 is shorted to connect Vee to Ve
so that negative supply is not present. S3’s are shorted by default but it has no effect on actual operation of the board.
Power scheme 5 - Similar to scheme 4 in terms of Vcc1 and DC/DC converter for Vcc2a. A second DC/DC converter at
IC2b with Vcc1 as Vin and +15V output at Vcc2b with reference to Veb. All S2’s are shorted to connect Vee to Ve so that
negative supplies are not present. S3’s are shorted by default but it has no effect on actual operation of the board.
This is necessary when IGBT or SiC/GaN MOSFETs get bigger demanding more driving power. Suitable for use when Qg
of IGBT or SiC/GaN MOSFET rises above 200nC.
(Bootstrapped power supplys can only handle low driving power.)
Power scheme 6 - Similar to scheme 5 with the use of Vcc1 and 2 DC/DC converters. However, each of the DC/DC con-
verters should have dual outputs set at ±15V to allow for the availability of negative Vee (at Veea & Veeb). Therefore, all
S2’s must be open, while all S3’s must be shorted.
Power scheme 7 - This scheme is useful if dual-output ±15V DC/DC converters are not available or dual-output ±9V DC/
DC converters are preferred. 15V Vcc2 can still be obtained using ±9V DC/DC converters by introducing a 15V zener at
D4 and R7 of around 1kOhm to provide proper biasing current at D4. For this scheme to work, both S2 and S3 jumpers
must be open. As the total voltage across Vcc2 with reference to Vee stays at 18V(=9V+9V), Vcc2 of 15V will be obtained
through the 15V D4 zener, and -3V at Vee, all with reference to virtual ground at Ve.
Using the Board
The evaluation board is easily prepared for use with only minor work being required (soldering cables for DC supplies,
proper cables for HVDC+/HVDC- high voltage bus, and load connections). The default connections of the evaluation
board when shipped to customers are shown in the Table 1.
Output Measurement
A sample of Input LED and various output waveforms are captured and shown in Figure 6 below. Default setup connec-
tion is adopted except with Q1a and Q1b IGBT or SiC/GaN MOSFETs mounted. The IGBT or SiC/GaN MOSFETs used have
a gate capacitance equivalent to 10nF.
Figure 6 also shows that once bootstrap supply is adopted, the output voltage amplitude at the top inverter arm will be
slightly less than the voltage at the bottom inverter arm, at 180
°
out of phase. (IN1+ is set at 49% duty ratio, while IN2+
(not shown) is also set with 49% duty ratio plus a turn-on delay of 100ns with reference to IN1+).
Figure 6. Input LED signal and IGBT or SiC/GaN MOSFET Gate Voltage Waveforms
IN1+
Vgs (Q1a)
Vgs (Q1b)
