7
Audial USB board
Mk2
THIS BOARD AND AYA II 2014 / DS
This board can be easily connected to AYA II DAC
projects released in 2014 and 2015 (DS).
Both USB board and AYA II 2014 / DS can operate in
both Philips simultaneous data and I2S mode. AYA II
2014 / DS can accept either simultaneous data
protocol or I2S at the input connectors J301-J304. At
the input connectors J305-J307 it can accept only I2S.
USB board output mode is defined by its firmware. AYA
II i.e. TDA1541A mode is set by TDA1541A pin 27, and
for simultaneous data mode it should be tied to -5
VDC (pin 26), whereas for I2S it should be tied to +5
VDC (pin 28). This can be done either by PCB DIP
switch or by wire jumper. Switch is recommended
though, so the mode can be easily changed later.
Preferred mode of operation is simultaneous data
mode, for better intrinsic jitter performance of
TDA1541(A).
Please however note also that the AYA II can not switch
automatically between two modes, so if you settle on
simultaneous data mode, you will have to change its
mode manually to I2S whenever the other input
(S/PDIF or external I2S) is used.
Before connecting this board to AYA II, the connection
between AYA II on-board USB stage and its input
switching relays must be cut. This can be done by
removing (or by pulling up one side of the) resistors
R118-R120. This way the U.FL connectors J301-J304
are ready to accept external source.
In addition, is also the good idea to turn AYA II on-
board USB stage completely off, by disconnecting its
secondary winding AC1.
In simultaneous data mode the connection between
two boards is achieved by four U.FL cables (Data L,
Data R, BCK, LE), while I2S requires three U.FL cables
(Data, BCK, WS).
By making these connections, the whole set-up is
ready for operation.
Two boards should be placed one beside the other,
into the same plane, and not one above the other.
AYA II 2014 / DS DEM CLOCKING
To determine right DEM clocking frequency, it is
important to know what sets its bottom and upper
limit. Firstly, a DEM clock frequency is divided by four
internally by TDA1541A, and this divided-by-four
frequency should never fall into the audio band,
because it can produce the glitches of its own. So,
practical bottom limit is 80 kHz. On the other side,
TDA1541A performance slightly decreases, as DEM
frequency increases. While this decrease is in fact not
huge, and occurs mostly at the bottom end of the
audio spectrum (0.5 dB at 100 Hz, for 400 kHz DEM
frequency), it is wise to keep the DEM frequency below
500 kHz.
The AYA II DS on-board DEM clocking circuit takes the
bit clock signal, and divides it by 16. This way, in
simultaneous data mode (32 bit frame) the DEM
frequency will be two times higher than audio
sampling frequency, while in I2S (64 bit frame) the
DEM frequency will be four times higher than audio
sampling frequency. In all these cases, and taking into
account the range of operation that applies to each
mode, the DEM frequency will always remain between
88.2 kHz and 384 kHz. Therefore, when AYA II DS is
used with this module, its DEM clocking circuit can be
left as is.
In the AYA II 2014 this synchronous DEM clocking
circuit is optional, but users can employ it the same
way it is used in the AYA II DS.
Of course, since this module offers also a master clock
output, this clock frequency, adequately scaled down,
can be also used as a basis for TDA1541A DEM circuit.
