5
Audial USB board
Mk2
OUTPUT FORMATS
Depending on the firmware, this board may output
one of the following digital protocols.
A. Philips simultaneous data protocol
This protocol is intended for use exclusively with
TDA1541(A). The output has split channels, 16-bit
right justified data, in offset binary format, clocked on
the falling edge of BCK. Negative data outputs are also
provided, so the board can be used as a source for true
balanced TDA1541(A) DAC.
B. I2S/ SPDIF
I2S is as specified, so two data channels are time
multiplexed, and binary word starts one BCK cycle
after WS transition. Data is in two’s complement
format, and is clocked on the raising edge of BCK. In
addition, the board with I2S output also has an S/PDIF
output.
C. PCM1704 format
Similarly to firmware A, this option has split channels,
and right justified data. The word is however 24-bit
long, data is in two’s complement format, and it is
clocked on the raising edge of BCK.
Output formats are graphically shown on the figure 4
(page 9).
OUTPUT CONNECTIONS
The table below shows detailed list of the signals
available on the set of nine U.FL connectors (J202 -
J210). The same applies to the BNC output connectors
of the completed unit, and the only exception is that
there is only one BNC connector per BCK and LE / WS
line.
In I2S mode, 75 Ohm S/PDIF output is available at BNC
connector J201, on the back side.
Connector
Output format
Simultaneous data
I2S / SPDIF
PCM1704
DL (J202 / J301)
Left channel data
x
Left channel data
DLN (J203 / J302)
Left channel inverted data
x
Left channel inverted data
DRN (J204 / J303)
Right channel inverted data
x
Right channel inverted data
DR / DATA (J205 / J304)
Right channel data
Data
Right channel data
BCK (J206 / J305)
Bit clock
Bit clock
Bit clock
BCK (J207)
Bit clock
Bit clock
Bit clock
LE / WS (J208 / J306)
Latch enable
Word select (a.k.a. LRCK)
Latch enable (WCLK)
LE / WS (J209)
Latch enable
Word select (a.k.a. LRCK)
Latch enable (WCLK)
MCK (J210 / J307)
Master clock
Master clock
Master clock
