Atmel XMEGA B, User Manual

Page: 214 / 415

214 XMEGA B [DATASHEET]
8291B–AVR–01/2013
18.4 SRAM Memory Mapping
The USB module uses internal SRAM to store the:

Endpoint configuration table

USB frame number

Transaction complete FIFO
The endpoint pointer register (EPPTR) is used to set the SRAM address for the endpoint configuration table. The USB
frame number (FRAMENUM) and transaction complete FIFO (FIFO) locations are derived from this. The locations of
these areas are selectable inside the internal SRAM.
Figure on page 214 gives the relative memory location of each
area.
Figure 18-6. SRAM memory mapping.
18.5 Clock Generation
The USB module requires a minimum 6MHz clock for USB low speed operation, and a minimum 48MHz clock for USB
full speed operation. It can be clocked from internal or external clock sources by using the internal PLL, or directly from
the 32MHz internal oscillator when it is tuned and calibrated to 48MHz. The CPU and peripherals clocks must run at a
minimum of 1.5MHz for low speed operation, and a minimum of 12MHz for full speed operation.
The USB module clock selection is independent of and separate from the main system clock selection. Selection and
setup are done using the main clock control settings. For details, refer to
“System Clock and Clock Options” on page 74 .
The Figure 18-7 on page 215 shows an overview of the USB module clock selection.
FIFO
EP_ADDRH_MAX
EP_ADDRL_0
EP_ADDRH_0
(MAXEP+1) x 4 Bytes
Active when FIFOEN==1
ENDPOINT
DESCRIPTORS
TABLE
STATUS
CTRL
CNTL
CNTH
DATAPTRL
DATAPTRH
AUXDATAL
AUXDATAH
ENDPOINT
0 OUT
STATUS
CTRL
CNTL
CNTH
DATAPTRL
DATAPTRH
AUXDATAL
AUXDATAH
ENDPOINT
0 IN
STATUS
CTRL
CNTL
CNTH
DATAPTRL
DATAPTRH
AUXDATAL
AUXDATAH
ENDPOINT
MAXEP IN
(MAXEP+1) x 16 Bytes
FRAME
NUMBER
FRAMENUML
FRAMENUMH
2 Bytes
Active when
STFRNUM==1
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
(MAXEP+1)<<4
EPPTR
EPPTR +
(MAXEP+1)*16
SRAM
ADDRESS