Atmel DataFlash AT45DB321 Page 13 Operation Download | Manualshive

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AT45DB321

13

Detailed Bit-level Read Timing – Inactive Clock Polarity Low

Main Memory Page Read

Buffer Read

Status Register Read

SI

0

1

0

1

0

X

X

X

CS

SO

SCK

1

2

3

4

5

60

61

62

63

64

65

66

67

X

X

HIGH-IMPEDANCE

D7

D6

D5

DATA OUT

COMMAND OPCODE

MSB

tSU

tV

SI

0

1

0

1

0

X

X

X

CS

SO

SCK

1

2

3

4

5

36

37

38

39

40

41

42

43

X

X

HIGH-IMPEDANCE

D7

D6

D5

DATA OUT

COMMAND OPCODE

MSB

tSU

tV

SI

0

1

0

1

0

1

1

1

CS

SO

SCK

1

2

3

4

5

7

8

9

10

11

12

16

17

HIGH-IMPEDANCE

D7

D6

D5

STATUS REGISTER OUTPUT

COMMAND OPCODE

MSB

tSU

tV

6

D1

D0

D7

LSB

MSB

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Summary of Contents for DataFlash AT45DB321

Page 1: ... only serial interface Flash memory suitable for in sys tem reprogramming Its 34 603 008 bits of memory are organized as 8192 pages of 528 bytes each In addition to the main memory the AT45DB321 also contains two SRAM data buffers of 528 bytes each The buffers allow receiving of data while a page in the main memory is being reprogrammed Unlike conventional Flash memo Rev 1121E 01 01 Pin Configurat...

Page 2: ...oltages for pro gramming The device operates from a single power sup ply 2 7V to 3 6V for both the program and read operations The AT45DB321 is enabled through the chip select pin CS and accessed via a three wire interface consisting of the Serial Input SI Serial Output SO and the Serial Clock SCK All programming cycles are self timed and no separate erase cycle is required before programming Bloc...

Page 3: ... pin The CS pin must remain low during the loading of the opcode the address bits and the reading of data When the end of a page in main memory is reached during a main memory page read the device will continue reading at the beginning of the same page A low to high transition on the CS pin will terminate the read operation and tri state the SO pin BUFFER READ Data can be read from either one of t...

Page 4: ...ry to be written and 10 addi tional don t care bits When a low to high transition occurs on the CS pin the part will first erase the selected page in main memory to all 1s and then program the data stored in the buffer into the specified page in the main memory Both the erase and the programming of the page are internally self timed and should take place in a maximum time of tEP During this time t...

Page 5: ...program the data from the buffer back into same page of main memory The operation is internally self timed and should take place in a maximum time of tEP During this time the status register will indicate that the part is busy If a sector is programmed or reprogrammed sequentially page by page then the programming algorithm shown in Figure 1 is recommended Otherwise if multiple bytes in a page or ...

Page 6: ...buffer 2 or vice versa See application note AN 4 Using Atmel s Serial DataFlash for more details HARDWARE PAGE WRITE PROTECT If the WP pin is held low the first 256 pages of the main memory cannot be reprogrammed The only way to reprogram the first 256 pages is to first drive the protect pin high and then use the program commands previously mentioned The WP pin is internally pulled high therefore ...

Page 7: ... only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Storage Temperature 65 C to 150 C All Input Voltages including NC Pins with Respect to Ground 0 6V to 6 25V All Output Voltages with Res...

Page 8: ...l Parameter Min Max Units fSCK SCK Frequency 13 MHz tWH SCK High Time 35 ns tWL SCK Low Time 35 ns tCS Minimum CS High Time 250 ns tCSS CS Setup Time 250 ns tCSH CS Hold Time 250 ns tCSB CS High to RDY BUSY Low 200 ns tSU Data In Setup Time 10 ns tH Data In Hold Time 20 ns tHO Output Hold Time 0 ns tDIS Output Disable Time 25 ns tV Output Valid 30 ns tXFR Page to Buffer Transfer Compare Time 350 µ...

Page 9: ...hold times for the SI signal are referenced to the low to high transition on the SCK signal Waveform 1 shows timing that is also compatible with SPI Mode 0 and Waveform 2 shows timing that is compatible with SPI Mode 3 Waveform 1 Inactive Clock Polarity Low Waveform 2 Inactive Clock Polarity High CS SCK SI SO tCSS VALID IN tH tSU tWH tWL tCSH tCS tV HIGH IMPEDANCE VALID OUT tHO tDIS HIGH IMPEDANCE...

Page 10: ...t r be a logical 0 for densities of 32M bit or smaller 3 For densities larger than 32M bit the r bits become the most significant Page Address bit for the appropriate density CS SCK RESET SO SI HIGH IMPEDANCE HIGH IMPEDANCE tRST tREC tCSS SI CMD 8 bits 8 bits 8 bits MSB Reserved for larger densities Page Address PA12 PA0 Byte Buffer Address BA9 BA0 BFA9 BFA0 LSB r X X X X X X X X X X X X X X X X X...

Page 11: ...IN MEMORY PAGE PROGRAM MAIN MEMORY PAGE PROGRAM THROUGH BUFFER 2 BUFFER 2 TO MAIN MEMORY PAGE PROGRAM MAIN MEMORY PAGE PROGRAM THROUGH BUFFER 1 BUFFER 1 WRITE BUFFER 2 WRITE SI CMD n n 1 Last Byte Completes writing into selected buffer Starts self timed erase program operation CS r PA12 6 PA5 0 BFA9 8 BFA7 0 SI CMD X X X BFA9 8 BFA7 0 n n 1 Last Byte Completes writing into selected buffer CS SI CM...

Page 12: ...RY ARRAY PAGE 528 BYTES BUFFER 2 528 BYTES BUFFER 1 528 BYTES I O INTERFACE MAIN MEMORY PAGE TO BUFFER 1 MAIN MEMORY PAGE TO BUFFER 2 MAIN MEMORY PAGE READ BUFFER 1 READ BUFFER 2 READ SO SI CMD PA5 0 BA9 8 BA7 0 X X X X CS n n 1 SO r PA12 6 SI CMD PA5 0 XX X Starts reading page data into buffer CS SO r PA12 6 SI CMD X X X BFA9 8 BFA7 0 CS n n 1 SO X n 1st byte read n 1 2nd byte read Each transitio...

Page 13: ...5 60 61 62 63 64 65 66 67 X X HIGH IMPEDANCE D7 D6 D5 DATA OUT COMMAND OPCODE MSB tSU tV SI 0 1 0 1 0 X X X CS SO SCK 1 2 3 4 5 36 37 38 39 40 41 42 43 X X HIGH IMPEDANCE D7 D6 D5 DATA OUT COMMAND OPCODE MSB tSU tV SI 0 1 0 1 0 1 1 1 CS SO SCK 1 2 3 4 5 7 8 9 10 11 12 16 17 HIGH IMPEDANCE D7 D6 D5 STATUS REGISTER OUTPUT COMMAND OPCODE MSB tSU tV 6 D1 D0 D7 LSB MSB ...

Page 14: ... 62 63 64 65 66 67 X X HIGH IMPEDANCE D7 D6 D5 DATA OUT COMMAND OPCODE MSB tSU tV D4 68 SI 0 1 0 1 0 X X X CS SO SCK 1 2 3 4 5 37 38 39 40 41 42 43 X X HIGH IMPEDANCE D7 D6 D5 DATA OUT COMMAND OPCODE MSB tSU tV D4 44 SI 0 1 0 1 0 1 1 1 CS SO SCK 1 2 3 4 5 7 8 9 10 11 12 17 18 HIGH IMPEDANCE D7 D6 D5 STATUS REGISTER OUTPUT COMMAND OPCODE MSB tSU tV 6 D4 D0 D7 LSB MSB D6 ...

Page 15: ...X PA10 X X PA10 PA10 PA10 PA10 X X PA9 X X PA9 PA9 PA9 PA9 X X PA8 X X PA8 PA8 PA8 PA8 X X PA7 X X PA7 PA7 PA7 PA7 X X PA6 X X PA6 PA6 PA6 PA6 X X PA5 X X PA5 PA5 PA5 PA5 X X PA4 X X PA4 PA4 PA4 PA4 X X PA3 X X PA3 PA3 PA3 PA3 X X PA2 X X PA2 PA2 PA2 PA2 X X PA1 X X PA1 PA1 PA1 PA1 X X PA0 X X PA0 PA0 PA0 PA0 X X BA9 BFA9 BFA9 X X X X BFA9 BFA9 BA8 BFA8 BFA8 X X X X BFA8 BFA8 BA7 BFA7 BFA7 X X X X...

Page 16: ... 0 0 0 0 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 1 r r r r r r r r r r PA12 PA12 PA12 PA12 PA12 PA12 PA12 PA12 PA12 PA12 PA11 PA11 PA11 PA11 PA11 PA11 PA11 PA11 PA11 PA11 PA10 PA10 PA10 PA10 PA10 PA10 PA10 PA10 PA10 PA10 PA9 PA9 PA9 PA9 PA9 PA9 PA9 PA9 PA9 PA9 PA8 PA8 PA8 PA8 PA8 PA8 PA8 PA8 PA8 PA8 PA7 PA7 PA7 PA7 PA7 PA7 PA7 PA7 PA7 PA7 PA6 PA6 PA6 PA6 PA6 PA6 PA6 PA6 PA6 PA6 PA5 PA5 PA5 PA5 PA5 PA5 PA5 P...

Page 17: ...e 2 A page can be written using either a Main Memory Page Program operation or a Buffer Write operation followed by a Buffer to Main Memory Page Program operation 3 The algorithm above shows the programming of a single page The algorithm will be repeated sequentially for each page within the entire sector START MAIN MEMORY PAGE PROGRAM 82H 85H END provide address and data BUFFER WRITE 84H 87H BUFF...

Page 18: ...mulative page erase program operations have accumulated before rewriting all pages of the sector See application note AN 4 Using Atmel s Serial DataFlash for more details Sector Addressing PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 Sector 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X X X X X X 1 0 0 0 1 X X X X X X 2 0 0 1 0 X X X X X X 3 1 1 0 0 X X X X X X 13 1 1 0 1 X X X X X X 14 1 1 1 0 X X X X X X 15 1 1 ...

Page 19: ...5 x 9 Array 1 0 mm Pitch Plastic Chip scale Ball Grid Array CBGA Ordering Information fSCK MHz ICC mA Ordering Code Package Operation Range Active Standby 13 10 0 01 AT45DB321 TC AT45DB321 CC 32T 44C1 Commercial 0 C to 70 C 13 10 0 01 AT45DB321 TI AT45DB321 CI 32T 44C1 Industrial 40 C to 85 C ...

Page 20: ... 295 REF 8 20 323 7 80 307 1 20 047 MAX 0 15 006 0 05 002 0 5 REF 0 70 028 0 50 020 0 20 008 0 10 004 44C1 44 ball 5 x 9 Array 1 0 mm Pitch Plastic Chip scale Ball Grid Array CBGA Dimensions in Millimeters and Inches Controlling dimension millimeters 6 2 0 244 5 8 0 228 12 2 0 480 11 8 0 465 1 20 0 047 MAX 0 30 0 012 A B C D E F G H J 1 00 0 039 BSC NON ACCUMULATIVE 0 41 0 016 DIA BALL TYP 4 0 0 1...

Page 21: ...ux 41 Casa Postale 80 CH 1705 Fribourg Switzerland TEL 41 26 426 5555 FAX 41 26 426 5500 Asia Atmel Asia Ltd Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL 852 2721 9778 FAX 852 2722 1369 Japan Atmel Japan K K 9F Tonetsu Shinkawa Bldg 1 24 8 Shinkawa Chuo ku Tokyo 104 0033 Japan TEL 81 3 3523 3551 FAX 81 3 3523 7581 Atmel Colorado Springs 1150 E Cheyenne Mtn Bl...

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