Atmel AVR ATmega168PA Manual Download | Manualshive

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8271D–AVR–05/11

ATmega48A/PA/88A/PA/168A/PA/328/P

Checker calculates the parity of the data bits in incoming frames and compares the result with
the parity bit from the serial frame. The result of the check is stored in the receive buffer together
with the received data and stop bits. The Parity Error (UPEn) Flag can then be read by software
to check if the frame had a Parity Error.

The UPEn bit is set if the next character that can be read from the receive buffer had a Parity
Error when received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is
valid until the receive buffer (UDRn) is read.

20.7.6

Disabling the Receiver

In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing
receptions will therefore be lost. When disabled (i.e., the RXENn is set to zero) the Receiver will
no longer override the normal function of the RxDn port pin. The Receiver buffer FIFO will be
flushed when the Receiver is disabled. Remaining data in the buffer will be lost

20.7.7

Flushing the Receive Buffer

The receiver buffer FIFO will be flushed when the Receiver is disabled, i.e., the buffer will be
emptied of its contents. Unread data will be lost. If the buffer has to be flushed during normal
operation, due to for instance an error condition, read the UDRn I/O location until the RXCn Flag
is cleared. The following code example shows how to flush the receive buffer.

Note:

1.

See ”About Code Examples” on page 8.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”
instructions must be replaced with instructions that allow access to extended I/O. Typically
“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.

20.8

Asynchronous Data Reception

The USART includes a clock recovery and a data recovery unit for handling asynchronous data
reception. The clock recovery logic is used for synchronizing the internally generated baud rate
clock to the incoming asynchronous serial frames at the RxDn pin. The data recovery logic sam-
ples and low pass filters each incoming bit, thereby improving the noise immunity of the
Receiver. The asynchronous reception operational range depends on the accuracy of the inter-
nal baud rate clock, the rate of the incoming frames, and the frame size in number of bits.

Assembly Code Example

USART_Flush:

in r16, UCSRnA

sbrs

r16, RXCn

ret

in

r16, UDRn

rjmp

USART_Flush

C Code Example

void

USART_Flush(

void

)

{

unsigned char

dummy;

while

( UCSRnA & (1<<RXCn) ) dummy = UDRn;

}

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Summary of Contents for AVR ATmega168PA

Page 1: ... Real Time Counter with Separate Oscillator Six PWM Channels 8 channel 10 bit ADC in TQFP and QFN MLF package Temperature Measurement 6 channel 10 bit ADC in PDIP Package Temperature Measurement Programmable Serial USART Master Slave SPI Serial Interface Byte oriented 2 wire Serial Interface Philips I2 C compatible Programmable Watchdog Timer with Separate On chip Oscillator On chip Analog Compara...

Page 2: ...8 PDIP 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 32 MLF Top View PCINT19 OC2B INT1 PD3 PCINT20 XCK T0 PD4 GND VCC GND VCC PCINT6 XTAL1 TOSC1 PB6 PCINT7 XTAL2 TOSC2 PB7 PC1 ADC1 PCINT9 PC0 ADC0 PCINT8 ADC7 GND AREF ADC6 AVCC PB5 SCK PCINT5 PCINT21 OC0B T1 PD5 PCINT22 OC0A AIN0 PD6 PCINT23 AIN1 PD7 PCINT0 CLKO ICP1 PB0 PCINT1 OC1A PB1 PCINT2 SS OC1B PB2 P...

Page 3: ... bi directional I O port with internal pull up resistors selected for each bit The PC5 0 output buffers have symmetrical drive characteristics with both high sink and source capability As inputs Port C pins that are externally pulled low will source current if the pull up resistors are activated The Port C pins are tri stated when a reset condition becomes active even if the clock is not running 1...

Page 4: ...xternally connected to VCC even if the ADC is not used If the ADC is used it should be connected to VCC through a low pass filter Note that PC6 4 use digital supply voltage VCC 1 1 8 AREF AREF is the analog reference pin for the A D Converter 1 1 9 ADC7 6 TQFP and QFN MLF Package Only In the TQFP and QFN MLF package ADC7 6 serve as analog inputs to the A D converter These pins are powered from the...

Page 5: ...2 1 Block Diagram The AVR core combines a rich instruction set with 32 general purpose working registers All the 32 registers are directly connected to the Arithmetic Logic Unit ALU allowing two independent registers to be accessed in one single instruction executed in one clock cycle The resulting PORT C 7 PORT B 8 PORT D 8 USART 0 8bit T C 2 16bit T C 1 8bit T C 0 A D Conv Internal Bandgap Analo...

Page 6: ...ocontrollers The patented charge transfer signal acquisition offers robust sensing and includes fully debounced reporting of touch keys and includes Adjacent Key Suppression AKS technology for unambiguous detection of key events The easy to use QTouch Suite toolchain allows you to explore develop and debug your own touch applications The device is manufactured using Atmel s high density non volati...

Page 7: ...t and no separate Boot Loader Section The SPM instruction can execute from the entire Flash ATmega88PA 8KBytes 512Bytes 1KBytes 1 instruction word vector ATmega168A 16KBytes 512Bytes 1KBytes 2 instruction words vector ATmega168PA 16KBytes 512Bytes 1KBytes 2 instruction words vector ATmega328 32KBytes 1KBytes 2KBytes 2 instruction words vector ATmega328P 32KBytes 1KBytes 2KBytes 2 instruction words...

Page 8: ...xtended I O map IN OUT SBIS SBIC CBI and SBI instructions must be replaced with instructions that allow access to extended I O Typically LDS and STS combined with SBRS SBRC SBR and CBR 6 Capacitive Touch Sensing The Atmel QTouch Library provides a simple to use solution to realize touch sensitive inter faces on most Atmel AVR microcontrollers The QTouch Library includes support for the Atmel QTouc...

Page 9: ...single level pipelining While one instruction is being executed the next instruc tion is pre fetched from the program memory This concept enables instructions to be executed in every clock cycle The program memory is In System Reprogrammable Flash memory The fast access Register File contains 32 x 8 bit general purpose working registers with a single clock cycle access time This allows single cycl...

Page 10: ...before subroutines or interrupts are executed The Stack Pointer SP is read write accessible in the I O space The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture The memory spaces in the AVR architecture are all linear and regular memory maps A flexible interrupt module has its control registers in the I O space with an additional Globa...

Page 11: ... desti nation for the operated bit A bit from a register in the Register File can be copied into T by the BST instruction and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction Bit 5 H Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations Half Carry Is useful in BCD arithmetic See the Instruction Set Description for de...

Page 12: ...rpose Working Registers Most of the instructions operating on the Register File have direct access to all registers and most of them are single cycle instructions As shown in Figure 7 2 each register is also assigned a data memory address mapping them directly into the first 32 locations of the user Data Space Although not being physically imple mented as SRAM locations this memory organization pr...

Page 13: ...mand will decrease the Stack Pointer The Stack in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled Initial Stack Pointer value equals the last address of the internal SRAM and the Stack Pointer must be set to point above start of the SRAM see Table 8 3 on page 19 See Table 7 1 for Stack Pointer details The AVR Stack Pointer is implemen...

Page 14: ...The Parallel Instruction Fetches and Instruction Executions Figure 7 5 shows the internal timing concept for the Register File In a single clock cycle an ALU operation using two register operands is executed and the result is stored back to the destina tion register Figure 7 5 Single Cycle ALU Operation Bit 15 14 13 12 11 10 9 8 0x3E 0x5E SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH 0x3D 0x5D SP7 SP6...

Page 15: ...utine The I bit is automatically set when a Return from Interrupt instruction RETI is executed There are basically two types of interrupts The first type is triggered by an event that sets the Interrupt Flag For these interrupts the Program Counter is vectored to the actual Interrupt Vec tor in order to execute the interrupt handling routine and hardware clears the corresponding Interrupt Flag Int...

Page 16: ... response time is increased by four clock cycles This increase comes in addition to the start up time from the selected sleep mode A return from an interrupt handling routine takes four clock cycles During these four clock cycles the Program Counter two bytes is popped back from the Stack the Stack Pointer is incremented by two and the I bit in SREG is set Assembly Code Example in r16 SREG store S...

Page 17: ...n Program Sec tion in ATmega88PA and ATmega168PA See SELFPRGEN description in section SPMCSR Store Program Memory Control and Status Register on page 295 for more details The Flash memory has an endurance of at least 10 000 write erase cycles The ATmega48A PA 88A PA 168A PA 328 P Program Counter PC is 11 12 13 14 bits wide thus addressing the 2 4 8 16K program memory locations The operation of Boo...

Page 18: ...am Memory Map ATmega 48A 48PA Figure 8 2 Program Memory Map ATmega88A ATmega88PA ATmega168A ATmega168PA ATmega328 and ATmega328P 0x0000 0x7FF Program Memory Application Flash Section 0x0000 0x0FFF 0x1FFF 0x3FFF Program Memory Application Flash Section Boot Flash Section ...

Page 19: ...or the data memory cover Direct Indirect with Displace ment Indirect Indirect with Pre decrement and Indirect with Post increment In the Register File registers R26 to R31 feature the indirect addressing pointer registers The direct addressing reaches the entire data space The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y or Z register When using...

Page 20: ... Registers are accessible in the I O space The write access time for the EEPROM is given in Table 8 2 A self timing function however lets the user software detect when the next byte can be written If the user code contains instruc tions that write the EEPROM some precautions must be taken In heavily filtered power supplies VCC is likely to rise or fall slowly on power up down This causes the devic...

Page 21: ...I Os and peripherals are placed in the I O space All I O locations may be accessed by the LD LDS LDD and ST STS STD instructions transferring data between the 32 general purpose working registers and the I O space I O Registers within the address range 0x00 0x1F are directly bit accessible using the SBI and CBI instructions In these registers the value of single bits can be checked by using the SB...

Page 22: ...A proper value must be written before the EEPROM may be accessed EEAR8 is an unused bit in ATmega 48A 48PA and must always be written to zero 8 6 2 EEDR The EEPROM Data Register Bits 7 0 EEDR 7 0 EEPROM Data For the EEPROM write operation the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register For the EEPROM read operation the EEDR contains the dat...

Page 23: ...er four clock cycles See the description of the EEPE bit for an EEPROM write procedure Bit 1 EEPE EEPROM Write Enable The EEPROM Write Enable Signal EEPE is the write strobe to the EEPROM When address and data are correctly set up the EEPE bit must be written to one to write the value into the EEPROM The EEMPE bit must be written to one before a logical one is written to EEPE other wise no EEPROM ...

Page 24: ...c one to trigger the EEPROM read The EEPROM read access takes one instruction and the requested data is available immediately When the EEPROM is read the CPU is halted for four cycles before the next instruction is executed The user should poll the EEPE bit before starting the read operation If a write operation is in progress it is neither possible to read the EEPROM nor to change the EEAR Regist...

Page 25: ...L r17 Write data r16 to Data Register out EEDR r16 Write logical one to EEMPE sbi EECR EEMPE Start eeprom write by setting EEPE sbi EECR EEPE ret C Code Example void EEPROM_write unsigned int uiAddress unsigned char ucData Wait for completion of previous write while EECR 1 EEPE Set up address and Data Registers EEAR uiAddress EEDR ucData Write logical one to EEMPE EECR 1 EEMPE Start eeprom write b...

Page 26: ...ter out EEARH r18 out EEARL r17 Start eeprom read by writing EERE sbi EECR EERE Read data from Data Register in r16 EEDR ret C Code Example unsigned char EEPROM_read unsigned int uiAddress Wait for completion of previous write while EECR 1 EEPE Set up address register EEAR uiAddress Start eeprom read by writing EERE EECR 1 EERE Return data from Data Register return EEDR Bit 7 6 5 4 3 2 1 0 0x2B 0x...

Page 27: ... by the majority of the I O modules like Timer Counters SPI and USART The I O clock is also used by the External Interrupt module but note that start condition detec tion in the USI module is carried out asynchronously when clkI O is halted TWI address recognition in all sleep modes Note Note that if a level triggered interrupt is used for wake up from Power down the required level must be held lo...

Page 28: ... 2 1 Default Clock Source The device is shipped with internal RC oscillator at 8 0MHz and with the fuse CKDIV8 pro grammed resulting in 1 0MHz system clock The startup time is set to maximum and time out period enabled CKSEL 0010 SUT 10 CKDIV8 0 The default setting ensures that all users can make their desired clock source setting using any available programming interface 9 2 2 Clock Startup Seque...

Page 29: ...t up sequence for the clock includes both the time out delay and the start up time when the device starts up from reset When starting up from Power save or Power down mode VCC is assumed to be at a sufficient level and only the start up time is included 9 3 Low Power Crystal Oscillator Pins XTAL1 and XTAL2 are input and output respectively of an inverting amplifier which can be configured for use ...

Page 30: ...he frequency specification of the device The CKSEL0 Fuse together with the SUT1 0 Fuses select the start up times as shown in Table 9 4 Table 9 3 Low Power Crystal Oscillator Operating Modes 3 Frequency Range MHz Recommended Range for Capacitors C1 and C2 pF CKSEL3 1 1 0 4 0 9 100 2 0 9 3 0 12 22 101 3 0 8 0 12 22 110 8 0 16 0 12 22 111 Table 9 4 Start up Times for the Low Power Crystal Oscillator...

Page 31: ...l only operate for VCC 2 7 5 5 volts C1 and C2 should always be equal for both crystals and resonators The optimal value of the capacitors depends on the crystal or resonator in use the amount of stray capacitance and the electromagnetic noise of the environment Some initial guidelines for choosing capacitors for use with crystals are given in Table 9 6 on page 32 For ceramic resonators the capaci...

Page 32: ...ility at start up is not important for the application Table 9 6 Start up Times for the Full Swing Crystal Oscillator Clock Selection Oscillator Source Power Conditions Start up Time from Power down and Power save Additional Delay from Reset VCC 5 0V CKSEL0 SUT1 0 Ceramic resonator fast rising power 258 CK 14CK 4 1ms 1 0 00 Ceramic resonator slowly rising power 258 CK 14CK 65ms 1 0 01 Ceramic reso...

Page 33: ... is the pin capacitance in Table 9 8 CL is the load capacitance for a 32 768kHz crystal specified by the crystal vendor CS is the total stray capacitance for one TOSC pin Crystals specifying load capacitance CL higher than 6 pF require external capacitors applied as described in Figure 9 2 on page 30 The Low frequency Crystal Oscillator must be selected by setting the CKSEL Fuses to 0110 or 0111 a...

Page 34: ...10 on page 323 When this Oscillator is used as the chip clock the Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset Time out For more information on the pre programmed cali bration value see the section Calibration Byte on page 302 Notes 1 The device is shipped with this option selected 2 If 8MHz frequency exceeds the specification of the device depends on VCC the CKD...

Page 35: ...e entered 9 8 External Clock To drive the device from an external clock source XTAL1 should be driven as shown in Figure 9 4 To run the device on an external clock the CKSEL Fuses must be programmed to 0000 see Table 9 15 Figure 9 4 External Clock Drive Configuration When this clock source is selected start up times are determined by the SUT Fuses as shown in Table 9 16 Table 9 13 128kHz Internal ...

Page 36: ...on page 33 for details on the oscillator and crystal requirements ATmega48A PA 88A PA 168A PA 328 P share the Timer Counter Oscillator Pins TOSC1 and TOSC2 with XTAL1 and XTAL2 When using the Timer Counter Oscillator the system clock needs to be four times the oscillator frequency Due to this and the pin sharing the Timer Coun ter Oscillator can only be used when the Calibrated Internal RC Oscilla...

Page 37: ...dable and the exact time it takes to switch from one clock division to the other cannot be exactly predicted From the time the CLKPS values are written it takes between T1 T2 and T1 2 T2 before the new clock frequency is active In this interval 2 active clock edges are produced Here T1 is the pre vious clock period and T2 is the period corresponding to the new prescaler setting To avoid unintentio...

Page 38: ...ency than OSCCAL 0x80 The CAL6 0 bits are used to tune the frequency within the selected range A setting of 0x00 gives the lowest frequency in that range and a setting of 0x7F gives the highest frequency in the range 9 12 2 CLKPR Clock Prescale Register Bit 7 CLKPCE Clock Prescaler Change Enable The CLKPCE bit must be written to logic one to enable change of the CLKPS bits The CLKPCE bit is only u...

Page 39: ...any value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting The Application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions The device is shipped with the CKDIV8 Fuse programmed Table 9 17 Clock Prescaler Select CLKPS3 CLKPS2 CLKPS1 ...

Page 40: ...the six sleep modes the SE bit in SMCR must be written to logic one and a SLEEP instruction must be executed The SM2 SM1 and SM0 bits in the SMCR Register select which sleep mode Idle ADC Noise Reduction Power down Power save Standby or Extended Standby will be activated by the SLEEP instruction See Table 10 2 on page 45 for a summary If an enabled interrupt occurs while the MCU is in a sleep mode...

Page 41: ...r ADC 2 wire Serial Interface Timer Counters Watchdog and the interrupt system to continue operating This sleep mode basically halts clkCPU and clkFLASH while allowing the other clocks to run Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow and USART Transmit Complete interrupts If wake up from the Analog Comparator interrupt ...

Page 42: ... to restart and become stable after having been stopped The wake up period is defined by the same CKSEL Fuses that define the Reset Time out period as described in Clock Sources on page 28 10 6 Power save Mode When the SM2 0 bits are written to 011 the SLEEP instruction makes the MCU enter Power save mode This mode is identical to Power down with one exception If Timer Counter2 is enabled it will ...

Page 43: ...as few as possible of the device s functions are operat ing All functions not needed should be disabled In particular the following modules may need special consideration when trying to achieve the lowest possible power consumption 10 10 1 Analog to Digital Converter If enabled the ADC will be enabled in all sleep modes To save power the ADC should be dis abled before entering any sleep mode When ...

Page 44: ...ant is then to ensure that no pins drive resistive loads In sleep modes where both the I O clock clkI O and the ADC clock clkADC are stopped the input buffers of the device will be disabled This ensures that no power is consumed by the input logic when not needed In some cases the input logic is needed for detecting wake up conditions and it will then be enabled Refer to the section Digital Input ...

Page 45: ...crystals or resonators Bit 0 SE Sleep Enable The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed To avoid the MCU entering the sleep mode unless it is the programmer s purpose it is recommended to write the Sleep Enable SE bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up Bit 7 6...

Page 46: ...Bit 7 PRTWI Power Reduction TWI Writing a logic one to this bit shuts down the TWI by stopping the clock to the module When waking up the TWI again the TWI should be re initialized to ensure proper operation Bit 6 PRTIM2 Power Reduction Timer Counter2 Writing a logic one to this bit shuts down the Timer Counter2 module in synchronous mode AS2 is 0 When the Timer Counter2 is enabled operation will ...

Page 47: ...waking up the SPI again the SPI should be re initialized to ensure proper operation Bit 1 PRUSART0 Power Reduction USART0 Writing a logic one to this bit shuts down the USART by stopping the clock to the module When waking up the USART again the USART should be re initialized to ensure proper operation Bit 0 PRADC Power Reduction ADC Writing a logic one to this bit shuts down the ADC The ADC must ...

Page 48: ...efines the electrical parameters of the reset circuitry The I O ports of the AVR are immediately reset to their initial state when a reset source goes active This does not require any clock source to be running After all reset sources have gone inactive a delay counter is invoked stretching the internal reset This allows the power to reach a stable level before normal operation starts The time out...

Page 49: ...eset POR circuit ensures that the device is reset from Power on Reaching the Power on Reset threshold voltage invokes the delay counter which determines how long the device is kept in RESET after VCC rise The RESET signal is activated again without any delay when VCC decreases below the detection level Figure 11 2 MCU Start up RESET Tied to VCC MCU Status Register MCUSR Brown out Reset Circuit BOD...

Page 50: ...A PA 168A PA 328 P has an On chip Brown out Detection BOD circuit for monitoring the VCC level during operation by comparing it to a fixed trigger level The trigger level for the BOD can be selected by the BODLEVEL Fuses The trigger level has a hysteresis to ensure spike free Brown out Detection The hysteresis on the detection level should be inter preted as VBOT VBOT VHYST 2 and VBOT VBOT VHYST 2...

Page 51: ...s an input to the Analog Comparator or the ADC 11 7 1 Voltage Reference Enable Signals and Start up Time The voltage reference has a start up time that may influence the way it should be used The start up time is given in System and Reset Characteristics on page 324 To save power the reference is not always turned on The reference is on during the following situations 1 When the BOD is enabled by ...

Page 52: ...sn t restart the counter an interrupt or system reset will be issued Figure 11 7 Watchdog Timer In Interrupt mode the WDT gives an interrupt when the timer expires This interrupt can be used to wake the device from sleep modes and also as a general system timer One example is to limit the maximum time allowed for certain operations giving an interrupt when the operation has run longer than expecte...

Page 53: ...dog change enable bit WDCE and WDE A logic one must be written to WDE regardless of the previous value of the WDE bit 2 Within the next four clock cycles write the WDE and Watchdog prescaler bits WDP as desired but with the WDCE bit cleared This must be done in one operation The following code example shows one assembly and one C function for turning off the Watch dog Timer The example assumes tha...

Page 54: ...e initialization routine even if the Watchdog is not in use Assembly Code Example 1 WDT_off Turn off global interrupt cli Reset Watchdog Timer wdr Clear WDRF in MCUSR in r16 MCUSR andi r16 0xff 0 WDRF out MCUSR r16 Write logical one to WDCE and WDE Keep old prescaler setting to prevent unintentional time out lds r16 WDTCSR ori r16 1 WDCE 1 WDE sts WDTCSR r16 Turn off WDT ldi r16 0 WDE sts WDTCSR r...

Page 55: ...ode Example 1 WDT_Prescaler_Change Turn off global interrupt cli Reset Watchdog Timer wdr Start timed sequence lds r16 WDTCSR ori r16 1 WDCE 1 WDE sts WDTCSR r16 Got four cycles to set the new values from here Set new prescaler time out value 64K cycles 0 5 s ldi r16 1 WDE 1 WDP2 1 WDP0 sts WDTCSR r16 Finished setting new values used 2 cycles Turn on global interrupt sei ret C Code Example 1 void ...

Page 56: ...gram If the register is cleared before another reset occurs the source of the reset can be found by examining the Reset Flags 11 9 2 WDTCSR Watchdog Timer Control Register Bit 7 WDIF Watchdog Interrupt Flag This bit is set when a time out occurs in the Watchdog Timer and the Watchdog Timer is config ured for interrupt WDIF is cleared by hardware when executing the corresponding interrupt handling ...

Page 57: ...hdog System Reset Enable WDE is overridden by WDRF in MCUSR This means that WDE is always set when WDRF is set To clear WDE WDRF must be cleared first This feature ensures multiple resets during con ditions causing failure and a safe start up after the failure Bit 5 2 0 WDP 3 0 Watchdog Timer Prescaler 3 2 1 and 0 The WDP 3 0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is ...

Page 58: ... 0 0 0 512K 524288 cycles 4 0 s 1 0 0 1 1024K 1048576 cycles 8 0 s 1 0 1 0 Reserved 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Table 11 2 Watchdog Timer Prescale Select Continued WDP3 WDP2 WDP1 WDP0 Number of WDT Oscillator Cycles Typical Time out at VCC 5 0V ...

Page 59: ...mega48PA Vector No Program Address Source Interrupt Definition 1 0x000 RESET External Pin Power on Reset Brown out Reset and Watchdog System Reset 2 0x001 INT0 External Interrupt Request 0 3 0x002 INT1 External Interrupt Request 1 4 0x003 PCINT0 Pin Change Interrupt Request 0 5 0x004 PCINT1 Pin Change Interrupt Request 1 6 0x005 PCINT2 Pin Change Interrupt Request 2 7 0x006 WDT Watchdog Time out I...

Page 60: ...r0 Compare A Handler 0x00F rjmp TIM0_COMPB Timer0 Compare B Handler 0x010 rjmp TIM0_OVF Timer0 Overflow Handler 0x011 rjmp SPI_STC SPI Transfer Complete Handler 0x012 rjmp USART_RXC USART RX Complete Handler 0x013 rjmp USART_UDRE USART UDR Empty Handler 0x014 rjmp USART_TXC USART TX Complete Handler 0x015 rjmp ADC ADC Conversion Complete Handler 0x016 rjmp EE_RDY EEPROM Ready Handler 0x017 rjmp AN...

Page 61: ... Interrupt Definition 1 0x000 1 RESET External Pin Power on Reset Brown out Reset and Watchdog System Reset 2 0x001 INT0 External Interrupt Request 0 3 0x002 INT1 External Interrupt Request 1 4 0x003 PCINT0 Pin Change Interrupt Request 0 5 0x004 PCINT1 Pin Change Interrupt Request 1 6 0x005 PCINT2 Pin Change Interrupt Request 2 7 0x006 WDT Watchdog Time out Interrupt 8 0x007 TIMER2 COMPA Timer Cou...

Page 62: ...TIM1_OVF Timer1 Overflow Handler 0x00E rjmp TIM0_COMPA Timer0 Compare A Handler 0x00F rjmp TIM0_COMPB Timer0 Compare B Handler 0x010 rjmp TIM0_OVF Timer0 Overflow Handler 0x011 rjmp SPI_STC SPI Transfer Complete Handler 0x012 rjmp USART_RXC USART RX Complete Handler 0x013 rjmp USART_UDRE USART UDR Empty Handler 0x014 rjmp USART_TXC USART TX Complete Handler 0x015 rjmp ADC ADC Conversion Complete H...

Page 63: ...cal and general program setup for the Reset and Interrupt Vector Addresses in ATmega88A 88PA is Address Labels Code Comments org 0x001 0x001 rjmp EXT_INT0 IRQ0 Handler 0x002 rjmp EXT_INT1 IRQ1 Handler 0x019 rjmp SPM_RDY Store Program Memory Ready Handler org 0xC00 0xC00 RESET ldi r16 high RAMEND Main program start 0xC01 out SPH r16 Set Stack Pointer to top of RAM 0xC02 ldi r16 low RAMEND 0xC03 out...

Page 64: ...est 0 3 0x0004 INT1 External Interrupt Request 1 4 0x0006 PCINT0 Pin Change Interrupt Request 0 5 0x0008 PCINT1 Pin Change Interrupt Request 1 6 0x000A PCINT2 Pin Change Interrupt Request 2 7 0x000C WDT Watchdog Time out Interrupt 8 0x000E TIMER2 COMPA Timer Counter2 Compare Match A 9 0x0010 TIMER2 COMPB Timer Counter2 Compare Match B 10 0x0012 TIMER2 OVF Timer Counter2 Overflow 11 0x0014 TIMER1 C...

Page 65: ...OMPA Timer2 Compare A Handler 0x0010 jmp TIM2_COMPB Timer2 Compare B Handler 0x0012 jmp TIM2_OVF Timer2 Overflow Handler 0x0014 jmp TIM1_CAPT Timer1 Capture Handler 0x0016 jmp TIM1_COMPA Timer1 Compare A Handler 0x0018 jmp TIM1_COMPB Timer1 Compare B Handler 0x001A jmp TIM1_OVF Timer1 Overflow Handler 0x001C jmp TIM0_COMPA Timer0 Compare A Handler 0x001E jmp TIM0_COMPB Timer0 Compare B Handler 0x0...

Page 66: ...IRQ0 Handler 0x1C04 jmp EXT_INT1 IRQ1 Handler 0x1C32 jmp SPM_RDY Store Program Memory Ready Handler When the BOOTRST Fuse is programmed and the Boot section size set to 2Kbytes the most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega168A 168PA is Address Labels Code Comments org 0x0002 0x0002 jmp EXT_INT0 IRQ0 Handler 0x0004 jmp EXT_INT1 IRQ1 Handler 0x0032...

Page 67: ...x0002 INT0 External Interrupt Request 0 3 0x0004 INT1 External Interrupt Request 1 4 0x0006 PCINT0 Pin Change Interrupt Request 0 5 0x0008 PCINT1 Pin Change Interrupt Request 1 6 0x000A PCINT2 Pin Change Interrupt Request 2 7 0x000C WDT Watchdog Time out Interrupt 8 0x000E TIMER2 COMPA Timer Counter2 Compare Match A 9 0x0010 TIMER2 COMPB Timer Counter2 Compare Match B 10 0x0012 TIMER2 OVF Timer Co...

Page 68: ...tup for the Reset and Interrupt Vector Addresses in ATmega328 328P is Address Labels Code Comments 0x0000 jmp RESET Reset Handler 0x0002 jmp EXT_INT0 IRQ0 Handler 0x0004 jmp EXT_INT1 IRQ1 Handler 0x0006 jmp PCINT0 PCINT0 Handler 0x0008 jmp PCINT1 PCINT1 Handler 0x000A jmp PCINT2 PCINT2 Handler 0x000C jmp WDT Watchdog Timer Handler 0x000E jmp TIM2_COMPA Timer2 Compare A Handler 0x0010 jmp TIM2_COMP...

Page 69: ...0037 sei Enable interrupts 0x0038 instr xxx When the BOOTRST Fuse is unprogrammed the Boot section size set to 2Kbytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled the most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega328 328P is Address Labels Code Comments 0x0000 RESET ldi r16 high RAMEND Main program start 0x0001 out...

Page 70: ... sei Enable interrupts 0x3C38 instr xxx 12 5 Register Description 12 5 1 Moving Interrupts Between Application and Boot Space ATmega88A 88PA ATmega168A 168PA and ATmega328 328P The MCU Control Register controls the placement of the Interrupt Vector table MCUCR MCU Control Register Note 1 BODS and BODSE only available for picoPower devices ATmega48PA 88PA 168PA 328P Bit 1 IVSEL Interrupt Vector Sel...

Page 71: ... If Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is programed interrupts are disabled while executing from the Boot Loader section Refer to the section Boot Loader Support Read While Write Self Programming on page 280 for details on Boot Lock bits Bit 0 IVCE Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit...

Page 72: ...1 interrupts are enabled and are configured as level triggered the inter rupts will trigger as long as the pin is held low Note that recognition of falling or rising edge interrupts on INT0 or INT1 requires the presence of an I O clock described in Clock Systems and their Distribution on page 27 Low level interrupt on INT0 and INT1 is detected asynchro nously This implies that this interrupt can b...

Page 73: ...activated by the external pin INT0 if the SREG I flag and the corre sponding interrupt mask are set The level and edges on the external INT0 pin that activate the interrupt are defined in Table 13 2 The value on the INT0 pin is sampled before detecting edges If edge or toggle interrupt is selected pulses that last longer than one clock period will generate an interrupt Shorter pulses are not guara...

Page 74: ...equest even if INT0 is configured as an output The corresponding interrupt of External Interrupt Request 0 is executed from the INT0 Interrupt Vector 13 2 3 EIFR External Interrupt Flag Register Bit 7 2 Reserved These bits are unused bits in the ATmega48A PA 88A PA 168A PA 328 P and will always read as zero Bit 1 INTF1 External Interrupt Flag 1 When an edge or logic change on the INT1 pin triggers...

Page 75: ...ge on any enabled PCINT 7 0 pin will cause an inter rupt The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Interrupt Vector PCINT 7 0 pins are enabled individually by the PCMSK0 Register 13 2 5 PCIFR Pin Change Interrupt Flag Register Bit 7 3 Reserved These bits are unused bits in the ATmega48A PA 88A PA 168A PA 328 P and will always read as zero Bit 2 PCIF2 Pin...

Page 76: ...Pin Change Enable Mask 14 8 Each PCINT 14 8 bit selects whether pin change interrupt is enabled on the corresponding I O pin If PCINT 14 8 is set and the PCIE1 bit in PCICR is set pin change interrupt is enabled on the corresponding I O pin If PCINT 14 8 is cleared pin change interrupt on the corresponding I O pin is disabled 13 2 8 PCMSK0 Pin Change Mask Register 0 Bit 7 0 PCINT 7 0 Pin Change En...

Page 77: ...rt and a lower case n represents the bit number However when using the register or bit defines in a program the precise form must be used For example PORTB3 for bit no 3 in Port B here documented generally as PORTxn The physical I O Regis ters and bit locations are listed in Register Description on page 94 Three I O memory address locations are allocated for each port one each for the Data Registe...

Page 78: ...e DDRx I O address the PORTxn bits at the PORTx I O address and the PINxn bits at the PINx I O address The DDxn bit in the DDRx Register selects the direction of this pin If DDxn is written logic one Pxn is configured as an output pin If DDxn is written logic zero Pxn is configured as an input pin If PORTxn is written logic one when the pin is configured as an input pin the pull up resistor is act...

Page 79: ... dis able all pull ups in all ports Switching between input with pull up and output low generates the same problem The user must use either the tri state DDxn PORTxn 0b00 or the output high state DDxn PORTxn 0b11 as an intermediate step Table 14 1 summarizes the control signals for the pin value 14 2 4 Reading the Pin Value Independent of the setting of Data Direction bit DDxn the port pin can be ...

Page 80: ... When reading back a software assigned pin value a nop instruction must be inserted as indi cated in Figure 14 4 The out instruction sets the SYNC LATCH signal at the positive edge of the clock In this case the delay tpd through the synchronizer is 1 system clock period Figure 14 4 Synchronization when Reading a Software Assigned Pin Value The following code example shows how to set port B pins 0 ...

Page 81: ...described in Alternate Port Functions on page 82 If a logic high level one is present on an asynchronous external interrupt pin configured as Interrupt on Rising Edge Falling Edge or Any Logic Change on Pin while the external interrupt is not enabled the corresponding External Interrupt Flag will be set when resuming from the above mentioned Sleep mode as the clamping in these sleep mode produces ...

Page 82: ...re serves as a generic description applicable to all port pins in the AVR microcontroller family Figure 14 5 Alternate Port Functions 1 Note 1 WRx WPx WDx RRx RPx and RDx are common to all pins within the same port clkI O SLEEP and PUD are common to all ports All other signals are unique for each pin clk RPx RRx WRx RDx WDx PUD SYNCHRONIZER WDx WRITE DDRx WRx WRITE PORTx RRx READ PORTx REGISTER RP...

Page 83: ...e Output Driver is enabled disabled when DDOV is set cleared regardless of the setting of the DDxn Register bit PVOE Port Value Override Enable If this signal is set and the Output Driver is enabled the port value is controlled by the PVOV signal If PVOE is cleared and the Output Driver is enabled the port Value is controlled by the PORTxn Register bit PVOV Port Value Override Value If PVOE is set...

Page 84: ...nd PINB7 will all read 0 XTAL1 TOSC1 PCINT6 Port B Bit 6 XTAL1 Chip clock Oscillator pin 1 Used for all chip clock sources except internal calibrated RC Oscillator When used as a clock pin the pin can not be used as an I O pin TOSC1 Timer Oscillator pin 1 Used only if internal calibrated RC Oscillator is selected as chip clock source and the asynchronous timer is enabled by the correct setting in ...

Page 85: ...OSI SPI Master Data output Slave Data input for SPI channel When the SPI is enabled as a Slave this pin is configured as an input regardless of the setting of DDB3 When the SPI is enabled as a Master the data direction of this pin is controlled by DDB3 When the pin is forced by the SPI to be an input the pull up can still be controlled by the PORTB3 bit OC2 Output Compare Match Output The PB3 pin ...

Page 86: ...t B to the overriding signals shown in Figure 14 5 on page 82 SPI MSTR INPUT and SPI SLAVE OUTPUT consti tute the MISO signal while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT Notes 1 INTRC means that one of the internal RC Oscillators are selected by the CKSEL fuses EXTCK means that external clock is selected by the CKSEL fuses Table 14 4 Overriding Signals for Alternate Functions in...

Page 87: ...0 PCINT2 PCIE0 PCINT1 PCIE0 PCINT0 PCIE0 DIEOV 1 1 1 1 DI PCINT3 INPUT SPI SLAVE INPUT PCINT2 INPUT SPI SS PCINT1 INPUT PCINT0 INPUT ICP1 INPUT AIO Table 14 6 Port C Pins Alternate Functions Port Pin Alternate Function PC6 RESET Reset pin PCINT14 Pin Change Interrupt 14 PC5 ADC5 ADC Input Channel 5 SCL 2 wire Serial Bus Clock Line PCINT13 Pin Change Interrupt 13 PC4 ADC4 ADC Input Channel 4 SDA 2 ...

Page 88: ...n PC5 can also be used as ADC input Channel 5 Note that ADC input channel 5 uses digital power PCINT13 Pin Change Interrupt source 13 The PC5 pin can serve as an external interrupt source SDA ADC4 PCINT12 Port C Bit 4 SDA 2 wire Serial Interface Data When the TWEN bit in TWCR is set one to enable the 2 wire Serial Interface pin PC4 is disconnected from the port and becomes the Serial Data I O pin ...

Page 89: ... Figure 14 5 on page 82 Note 1 When enabled the 2 wire Serial Interface enables slew rate controls on the output pins PC4 and PC5 This is not shown in the figure In addition spike filters are connected between the AIO outputs shown in the port figure and the digital logic of the TWI module Table 14 7 Overriding Signals for Alternate Functions in PC6 PC4 1 Signal Name PC6 RESET PCINT14 PC5 SCL ADC5...

Page 90: ...0 INPUT Table 14 9 Port D Pins Alternate Functions Port Pin Alternate Function PD7 AIN1 Analog Comparator Negative Input PCINT23 Pin Change Interrupt 23 PD6 AIN0 Analog Comparator Positive Input OC0A Timer Counter0 Output Compare Match A Output PCINT22 Pin Change Interrupt 22 PD5 T1 Timer Counter 1 External Counter Input OC0B Timer Counter0 Output Compare Match B Output PCINT21 Pin Change Interrup...

Page 91: ...nterrupt source 22 The PD6 pin can serve as an external interrupt source T1 OC0B PCINT21 Port D Bit 5 T1 Timer Counter1 counter source OC0B Output Compare Match output The PD5 pin can serve as an external output for the Timer Counter0 Compare Match B The PD5 pin has to be configured as an output DDD5 set one to serve this function The OC0B pin is also the output pin for the PWM mode timer function...

Page 92: ...s pin is configured as an input regardless of the value of DDD0 When the USART forces this pin to be an input the pull up can still be controlled by the PORTD0 bit PCINT16 Pin Change Interrupt source 16 The PD0 pin can serve as an external interrupt source Table 14 10 and Table 14 11 relate the alternate functions of Port D to the overriding signals shown in Figure 14 5 on page 82 Table 14 10 Over...

Page 93: ... PD2 INT0 PCINT18 PD1 TXD PCINT17 PD0 RXD PCINT16 PUOE 0 0 TXEN RXEN PUO 0 0 0 PORTD0 PUD DDOE 0 0 TXEN RXEN DDOV 0 0 1 0 PVOE OC2B ENABLE 0 TXEN 0 PVOV OC2B 0 TXD 0 DIEOE INT1 ENABLE PCINT19 PCIE2 INT0 ENABLE PCINT18 PCIE1 PCINT17 PCIE2 PCINT16 PCIE2 DIEOV 1 1 1 1 DI PCINT19 INPUT INT1 INPUT PCINT18 INPUT INT0 INPUT PCINT17 INPUT PCINT16 INPUT RXD AIO ...

Page 94: ...e R R W R W R W R R R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 0x05 0x25 PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 PORTB Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 0x04 0x24 DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 DDRB Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 0x03 0x23...

Page 95: ...79 Bit 7 6 5 4 3 2 1 0 0x0B 0x2B PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 PORTD Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 0x0A 0x2A DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 DDRD Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 0x09 0x29 PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 PIND R...

Page 96: ... Counter module with two independent Output Compare Units and with PWM support It allows accurate program execution timing event man agement and wave generation A simplified block diagram of the 8 bit Timer Counter is shown in Figure 15 1 For the actual placement of I O pins refer to Pinout ATmega48A PA 88A PA 168A PA 328 P on page 2 CPU accessible I O Registers including I O bits and I O pins are...

Page 97: ...t registers Interrupt request abbreviated to Int Req in the figure signals are all visible in the Timer Interrupt Flag Register TIFR0 All interrupts are individually masked with the Timer Inter rupt Mask Register TIMSK0 TIFR0 and TIMSK0 are not shown in the figure Clock Select Timer Counter DATA BUS OCRnA OCRnB TCNTn Waveform Generation Waveform Generation OCnA OCnB Fixed TOP Value Control Logic 0...

Page 98: ... bits located in the Timer Counter Control Register TCCR0B For details on clock sources and pres caler see Timer Counter0 and Timer Counter1 Prescalers on page 143 15 4 Counter Unit The main part of the 8 bit Timer Counter is the programmable bi directional counter unit Figure 15 2 shows a block diagram of the counter and its surroundings Figure 15 2 Counter Unit Block Diagram Signal description i...

Page 99: ...lag generates an Output Compare interrupt The Output Compare Flag is automatically cleared when the interrupt is exe cuted Alternatively the flag can be cleared by software by writing a logical one to its I O bit location The Waveform Generator uses the match signal to generate an output according to operating mode set by the WGM02 0 bits and Compare Output mode COM0x1 0 bits The max and bottom si...

Page 100: ...t independently of whether the Timer Counter is running or not If the value written to TCNT0 equals the OCR0x value the compare match will be missed resulting in incorrect waveform generation Similarly do not write the TCNT0 value equal to BOTTOM when the counter is downcounting The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output The easi...

Page 101: ...egister is to be performed on the next compare match For compare output actions in the non PWM modes refer to Table 15 2 on page 108 For fast PWM mode refer to Table 15 3 on page 108 and for phase correct PWM refer to Table 15 4 on page 109 A change of the COM0x1 0 bits state will have effect at the first compare match after the bits are written For non PWM modes the action can be forced to have i...

Page 102: ...alue TCNT0 matches the OCR0A The OCR0A defines the top value for the counter hence also its resolution This mode allows greater control of the compare match output frequency It also simplifies the operation of counting external events The timing diagram for the CTC mode is shown in Figure 15 5 The counter value TCNT0 increases until a compare match occurs between TCNT0 and OCR0A and then counter T...

Page 103: ...e operation the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that use dual slope operation This high frequency makes the fast PWM mode well suited for power regulation rectification and DAC applications High frequency allows physically small sized external components coils capacitors and therefore reduces total system cost In fast PWM mode the counter...

Page 104: ... each compare match COM0x1 0 1 The waveform generated will have a maximum frequency of fOC0 fclk_I O 2 when OCR0A is set to zero This feature is similar to the OC0A toggle in CTC mode except the double buffer feature of the Out put Compare unit is enabled in the fast PWM mode 15 7 4 Phase Correct PWM Mode The phase correct PWM mode WGM02 0 1 or 5 provides a high resolution phase correct PWM wavefo...

Page 105: ...ng the OC0x Register at compare match between OCR0x and TCNT0 when the counter decrements The PWM frequency for the output when using phase correct PWM can be calculated by the following equation The N variable represents the prescale factor 1 8 64 256 or 1024 The extreme values for the OCR0A Register represent special cases when generating a PWM waveform output in the phase correct PWM mode If th...

Page 106: ...he following figures The figures include information on when interrupt flags are set Figure 15 8 contains timing data for basic Timer Counter operation The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode Figure 15 8 Timer Counter Timing Diagram no Prescaling Figure 15 9 shows the same timing data but with the prescaler enabled Figure 15 9 Timer...

Page 107: ...ws the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast PWM mode where OCR0A is TOP Figure 15 11 Timer Counter Timing Diagram Clear Timer on Compare Match mode with Pres caler fclk_I O 8 OCFnx OCRnx TCNTn OCRnx Value OCRnx 1 OCRnx OCRnx 1 OCRnx 2 clkI O clkTn clkI O 8 OCFnx OCRnx TCNTn CTC TOP TOP 1 TOP BOTTOM BOTTOM 1 clkI O clkTn clkI O 8 ...

Page 108: ...ionality when the WGM01 0 bits are set to fast PWM mode Note 1 A special case occurs when OCR0A equals TOP and COM0A1 is set In this case the Com pare Match is ignored but the set or clear is done at BOTTOM See Fast PWM Mode on page 103 for more details Bit 7 6 5 4 3 2 1 0 0x24 0x44 COM0A1 COM0A0 COM0B1 COM0B0 WGM01 WGM00 TCCR0A Read Write R W R W R W R W R R R W R W Initial Value 0 0 0 0 0 0 0 0 ...

Page 109: ... shows the COM0B1 0 bit functionality when the WGM02 0 bits are set to fast PWM mode Note 1 A special case occurs when OCR0B equals TOP and COM0B1 is set In this case the Com pare Match is ignored but the set or clear is done at TOP See Fast PWM Mode on page 103 for more details Table 15 4 Compare Output Mode Phase Correct PWM Mode 1 COM0A1 COM0A0 Description 0 0 Normal port operation OC0A disconn...

Page 110: ... operation supported by the Timer Counter unit are Normal mode counter Clear Timer on Compare Match CTC mode and two types of Pulse Width Modulation PWM modes see Modes of Operation on page 101 Notes 1 MAX 0xFF 2 BOTTOM 0x00 Table 15 7 Compare Output Mode Phase Correct PWM Mode 1 COM0B1 COM0B0 Description 0 0 Normal port operation OC0B disconnected 0 1 Reserved 1 0 Clear OC0B on Compare Match when...

Page 111: ... a non PWM mode However for ensuring compatibility with future devices this bit must be set to zero when TCCR0B is written when operating in PWM mode When writing a logical one to the FOC0B bit an immediate Compare Match is forced on the Waveform Generation unit The OC0B output is changed according to its COM0B1 0 bits setting Note that the FOC0B bit is implemented as a strobe Therefore it is the ...

Page 112: ...upt or to generate a waveform output on the OC0A pin 15 9 5 OCR0B Output Compare Register B The Output Compare Register B contains an 8 bit value that is continuously compared with the counter value TCNT0 A match can be used to generate an Output Compare interrupt or to generate a waveform output on the OC0B pin Table 15 9 Clock Select Bit Description CS02 CS01 CS00 Description 0 0 0 No clock sour...

Page 113: ...nding interrupt is executed if an overflow in Timer Counter0 occurs i e when the TOV0 bit is set in the Timer Counter 0 Inter rupt Flag Register TIFR0 15 9 7 TIFR0 Timer Counter 0 Interrupt Flag Register Bits 7 3 Reserved These bits are reserved bits in the ATmega48A PA 88A PA 168A PA 328 P and will always read as zero Bit 2 OCF0B Timer Counter 0 Output Compare B Match Flag The OCF0B bit is set wh...

Page 114: ...set when an overflow occurs in Timer Counter0 TOV0 is cleared by hardware when executing the corresponding interrupt handling vector Alternatively TOV0 is cleared by writing a logic one to the flag When the SREG I bit TOIE0 Timer Counter0 Overflow Interrupt Enable and TOV0 are set the Timer Counter0 Overflow interrupt is executed The setting of this flag is dependent of the WGM02 0 bit setting Ref...

Page 115: ...ng measurement Most register and bit references in this section are written in general form A lower case n replaces the Timer Counter number and a lower case x replaces the Output Compare unit channel However when using the register or bit defines in a program the precise form must be used i e TCNT1 for accessing Timer Counter1 counter value and so on A simplified block diagram of the 16 bit Timer...

Page 116: ... TIMSK1 TIFR1 and TIMSK1 are not shown in the figure The Timer Counter can be clocked internally via the prescaler or by an external clock source on the T1 pin The Clock Select logic block controls which clock source and edge the Timer Counter uses to increment or decrement its value The Timer Counter is inactive when no clock source is selected The output from the Clock Select logic is referred t...

Page 117: ...egister for temporary storing of the high byte of the 16 bit access The same temporary register is shared between all 16 bit registers within each 16 bit timer Accessing the low byte triggers the 16 bit read or write operation When the low byte of a 16 bit register is written by the CPU the high byte stored in the temporary register and the low byte written are both copied into the 16 bit register...

Page 118: ...the interrupt code updates the temporary register by accessing the same or any other of the 16 bit Timer Regis ters then the result of the access outside the interrupt will be corrupted Therefore when both the main code and the interrupt code update the temporary register the main code must disable the interrupts during the 16 bit access The following code examples show how to do an atomic read of...

Page 119: ... following code examples show how to do an atomic write of the TCNT1 Register contents Writing any of the OCR1A B or ICR1 Registers can be done by using the same principle Assembly Code Example 1 TIM16_ReadTCNT1 Save global interrupt flag in r18 SREG Disable interrupts cli Read TCNT1 into r17 r16 in r16 TCNT1L in r17 TCNT1H Restore global interrupt flag out SREG r18 ret C Code Example 1 unsigned i...

Page 120: ...f atomic operation described previously also applies in this case 16 4 Timer Counter Clock Sources The Timer Counter can be clocked by an internal or an external clock source The clock source is selected by the Clock Select logic which is controlled by the Clock Select CS12 0 bits located in the Timer Counter control Register B TCCR1B For details on clock sources and prescaler see Timer Counter0 a...

Page 121: ... counter value within one clock cycle via the 8 bit data bus It is important to notice that there are special cases of writing to the TCNT1 Register when the counter is counting that will give unpredictable results The special cases are described in the sections where they are of importance Depending on the mode of operation used the counter is cleared incremented or decremented at each timer cloc...

Page 122: ...ively on the Analog Comparator output ACO and this change confirms to the setting of the edge detector a capture will be triggered When a capture is triggered the 16 bit value of the counter TCNT1 is written to the Input Capture Register ICR1 The Input Capture Flag ICF1 is set at the same system clock as the TCNT1 value is copied into ICR1 Register If enabled ICIE1 1 the Input Capture Flag generat...

Page 123: ... improves noise immunity by using a simple digital filtering scheme The noise canceler input is monitored over four samples and all four must be equal for changing the output that in turn is used by the edge detector The noise canceler is enabled by setting the Input Capture Noise Canceler ICNC1 bit in Timer Counter Control Register B TCCR1B When enabled the noise canceler introduces addi tional f...

Page 124: ...of operation See Section 16 9 on page 127 A special feature of Output Compare unit A allows it to define the Timer Counter TOP value i e counter resolution In addition to the counter resolution the TOP value defines the period time for waveforms generated by the Waveform Generator Figure 16 4 shows a block diagram of the Output Compare unit The small n in the register and bit names indicates the d...

Page 125: ...it Forcing compare match will not set the OCF1x Flag or reload clear the timer but the OC1x pin will be updated as if a real compare match had occurred the COM11 0 bits settings define whether the OC1x pin is set cleared or toggled 16 7 2 Compare Match Blocking by TCNT1 Write All CPU writes to the TCNT1 Register will block any compare match that occurs in the next timer clock cycle even when the t...

Page 126: ... 0 bits are set However the OC1x pin direction input or out put is still controlled by the Data Direction Register DDR for the port pin The Data Direction Register bit for the OC1x pin DDR_OC1x must be set as output before the OC1x value is visi ble on the pin The port override function is generally independent of the Waveform Generation mode but there are some exceptions Refer to Table 16 1 Table...

Page 127: ...er Overflow Flag TOV1 will be set in the same timer clock cycle as the TCNT1 becomes zero The TOV1 Flag in this case behaves like a 17th bit except that it is only set not cleared However combined with the timer overflow interrupt that automatically clears the TOV1 Flag the timer resolution can be increased by soft ware There are no special cases to consider in the Normal mode a new counter value ...

Page 128: ...or the pin is set to output DDR_OC1A 1 The waveform generated will have a maximum fre quency of fOC1A fclk_I O 2 when OCR1A is set to zero 0x0000 The waveform frequency is defined by the following equation The N variable represents the prescaler factor 1 8 64 256 or 1024 As for the Normal mode of operation the TOV1 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x000...

Page 129: ... set at the same timer clock cycle as TOV1 is set when either OCR1A or ICR1 is used for defining the TOP value If one of the interrupts are enabled the interrupt han dler routine can be used for updating the TOP and compare values When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers If the TOP value is lower than...

Page 130: ...ut in the fast PWM mode If the OCR1x is set equal to BOTTOM 0x0000 the out put will be a narrow spike for each TOP 1 timer clock cycle Setting the OCR1x equal to TOP will result in a constant high or low output depending on the polarity of the output set by the COM1x1 0 bits A frequency with 50 duty cycle waveform output in fast PWM mode can be achieved by set ting OC1A to toggle its logical level...

Page 131: ...r Overflow Flag TOV1 is set each time the counter reaches BOTTOM When either OCR1A or ICR1 is used for defining the TOP value the OC1A or ICF1 Flag is set accord ingly at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value at TOP The Interrupt Flags can be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value When changing the TO...

Page 132: ...en generating a PWM waveform output in the phase correct PWM mode If the OCR1x is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be continuously high for non inverted PWM mode For inverted PWM the output will have the opposite logic values If OCR1A is used to define the TOP value WGM13 0 11 and COM1A1 0 1 the OC1A output will toggle with a 50 duty c...

Page 133: ...ure 16 9 Phase and Frequency Correct PWM Mode Timing Diagram The Timer Counter Overflow Flag TOV1 is set at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value at BOTTOM When either OCR1A or ICR1 is used for defining the TOP value the OC1A or ICF1 Flag set when TCNT1 has reached TOP The Interrupt Flags can then be used to generate an interrupt each time the c...

Page 134: ... using phase and frequency correct PWM can be calculated by the following equation The N variable represents the prescaler divider 1 8 64 256 or 1024 The extreme values for the OCR1x Register represents special cases when generating a PWM waveform output in the phase correct PWM mode If the OCR1x is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be ...

Page 135: ...timing diagrams will be the same but TOP should be replaced by BOTTOM TOP 1 by BOTTOM 1 and so on The same renaming applies for modes that set the TOV1 Flag at BOTTOM Figure 16 12 Timer Counter Timing Diagram no Prescaling OCFnx OCRnx TCNTn OCRnx Value OCRnx 1 OCRnx OCRnx 1 OCRnx 2 clkI O clkTn clkI O 8 TOVn FPWM and ICFn if used as TOP OCRnx Update at TOP TCNTn CTC and FPWM TCNTn PC and PFC PWM T...

Page 136: ...ata Direction Register DDR bit correspond ing to the OC1A or OC1B pin must be set in order to enable the output driver When the OC1A or OC1B is connected to the pin the function of the COM1x1 0 bits is depen dent of the WGM13 0 bits setting Table 16 1 shows the COM1x1 0 bit functionality when the WGM13 0 bits are set to a Normal or a CTC mode non PWM TOVn FPWM and ICFn if used as TOP OCRnx Update ...

Page 137: ...ounter unit are Normal mode counter Clear Timer on Compare match CTC mode and three types of Pulse Width Modulation PWM modes See Modes of Operation on page 127 Table 16 2 Compare Output Mode Fast PWM 1 COM1A1 COM1B1 COM1A0 COM1B0 Description 0 0 Normal port operation OC1A OC1B disconnected 0 1 WGM13 0 14 or 15 Toggle OC1A on Compare Match OC1B disconnected normal port operation For all other WGM1...

Page 138: ...ding to the ICES1 setting the counter value is copied into the Input Capture Register ICR1 The event will also set the Input Capture Flag ICF1 and this can be used to cause an Input Capture Interrupt if this interrupt is enabled Table 16 4 Waveform Generation Mode Bit Description 1 Mode WGM13 WGM12 CTC1 WGM11 PWM11 WGM10 PWM10 Timer Counter Mode of Operation TOP Update of OCR1x at TOV1 Flag Set on...

Page 139: ... Output Compare for Channel B The FOC1A FOC1B bits are only active when the WGM13 0 bits specifies a non PWM mode When writing a logical one to the FOC1A FOC1B bit an immediate compare match is forced on the Waveform Generation unit The OC1A OC1B output is changed according to its COM1x1 0 bits setting Note that the FOC1A FOC1B bits are implemented as strobes Therefore it is the value present in t...

Page 140: ...used to generate an Output Compare interrupt or to generate a waveform output on the OC1x pin The Output Compare Registers are 16 bit in size To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers the access is performed using an 8 bit temporary High Byte Register TEMP This temporary register is shared by all the other 16 bit registers See Acce...

Page 141: ...the Status Register is set interrupts globally enabled the Timer Counter1 Output Compare B Match interrupt is enabled The corresponding Interrupt Vector see Interrupts on page 59 is executed when the OCF1B Flag located in TIFR1 is set Bit 1 OCIE1A Timer Counter1 Output Compare A Match Interrupt Enable When this bit is written to one and the I flag in the Status Register is set interrupts globally ...

Page 142: ...CF1B is automatically cleared when the Output Compare Match B Interrupt Vector is exe cuted Alternatively OCF1B can be cleared by writing a logic one to its bit location Bit 1 OCF1A Timer Counter1 Output Compare A Match Flag This flag is set in the timer clock cycle after the counter TCNT1 value matches the Output Compare Register A OCR1A Note that a Forced Output Compare FOC1A strobe will not set...

Page 143: ... number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N 1 system clock cycles where N equals the prescaler divisor 8 64 256 or 1024 It is possible to use the prescaler reset for synchronizing the Timer Counter to program execu tion However care must be taken if the other Timer Counter that shares the same prescaler also uses prescaling A prescaler...

Page 144: ...given a 50 50 duty cycle Since the edge detector uses sampling the maximum frequency of an external clock it can detect is half the sampling fre quency Nyquist sampling theorem However due to variation of the system clock frequency and duty cycle caused by Oscillator source crystal resonator and capacitors tolerances it is recommended that maximum frequency of an external clock source is less than...

Page 145: ...be configured to the same value without the risk of one of them advancing during configuration When the TSM bit is written to zero the PSRASY and PSRSYNC bits are cleared by hardware and the Timer Counters start counting simultaneously Bit 0 PSRSYNC Prescaler Reset When this bit is one Timer Counter1 and Timer Counter0 prescaler will be Reset This bit is nor mally cleared immediately by hardware e...

Page 146: ...m of the 8 bit Timer Counter is shown in Figure 18 1 For the actual placement of I O pins refer to Pinout ATmega48A PA 88A PA 168A PA 328 P on page 2 CPU accessible I O Registers including I O bits and I O pins are shown in bold The device specific I O Register and bit locations are listed in the Register Description on page 160 The PRTIM2 bit in Minimizing Power Consumption on page 43 must be wri...

Page 147: ...st 18 2 2 Definitions Many register and bit references in this document are written in general form A lower case n replaces the Timer Counter number in this case 2 However when using the register or bit defines in a program the precise form must be used i e TCNT2 for accessing Timer Counter2 counter value and so on The definitions in Table 18 1 are also used extensively throughout the section Tabl...

Page 148: ...the Output Compare outputs OC2A and OC2B For more details about advanced counting sequences and waveform generation see Modes of Operation on page 151 The Timer Counter Overflow Flag TOV2 is set according to the mode of operation selected by the WGM22 0 bits TOV2 can be used for generating a CPU interrupt 18 5 Output Compare Unit The 8 bit comparator continuously compares TCNT2 with the Output Com...

Page 149: ... will not set the OCF2x Flag or reload clear the timer but the OC2x pin will be updated as if a real compare match had occurred the COM2x1 0 bits settings define whether the OC2x pin is set cleared or toggled 18 5 2 Compare Match Blocking by TCNT2 Write All CPU write operations to the TCNT2 Register will block any compare match that occurs in the next timer clock cycle even when the timer is stopp...

Page 150: ...d I O pins in the figure are shown in bold Only the parts of the general I O Port Control Registers DDR and PORT that are affected by the COM2x1 0 bits are shown When referring to the OC2x state the reference is for the internal OC2x Register not the OC2x pin Figure 18 4 Compare Match Output Unit Schematic The general I O port function is overridden by the Output Compare OC2x from the Waveform Gen...

Page 151: ... on page 155 18 7 1 Normal Mode The simplest mode of operation is the Normal mode WGM22 0 0 In this mode the counting direction is always up incrementing and no counter clear is performed The counter simply overruns when it passes its maximum 8 bit value TOP 0xFF and then restarts from the bot tom 0x00 In normal operation the Timer Counter Overflow Flag TOV2 will be set in the same timer clock cyc...

Page 152: ... 0x00 The waveform frequency is defined by the following equation The N variable represents the prescale factor 1 8 32 64 128 256 or 1024 As for the Normal mode of operation the TOV2 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x00 18 7 3 Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode WGM22 0 3 or 7 provides a high fre quency PWM waveform generatio...

Page 153: ...R2A when MGM2 0 7 See Table 18 3 on page 160 The actual OC2x value will only be visible on the port pin if the data direction for the port pin is set as output The PWM wave form is generated by setting or clearing the OC2x Register at the compare match between OCR2x and TCNT2 and clearing or setting the OC2x Register at the timer clock cycle the counter is cleared changes from TOP to BOTTOM The PW...

Page 154: ... the symmet ric feature of the dual slope PWM modes these modes are preferred for motor control applications In phase correct PWM mode the counter is incremented until the counter value matches TOP When the counter reaches TOP it changes the count direction The TCNT2 value will be equal to TOP for one timer clock cycle The timing diagram for the phase correct PWM mode is shown on Figure 18 7 The T...

Page 155: ...as a transition from high to low even though there is no Compare Match The point of this transition is to guarantee symmetry around BOT TOM There are two cases that give a transition without Compare Match OCR2A changes its value from MAX like in Figure 18 7 When the OCR2A value is MAX the OCn pin value is the same as the result of a down counting compare match To ensure symmetry around BOTTOM the ...

Page 156: ...tting of OCF2A with Prescaler fclk_I O 8 Figure 18 11 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode Figure 18 11 Timer Counter Timing Diagram Clear Timer on Compare Match mode with Pres caler fclk_I O 8 TOVn TCNTn MAX 1 MAX BOTTOM BOTTOM 1 clkI O clkTn clkI O 8 OCFnx OCRnx TCNTn OCRnx Value OCRnx 1 OCRnx OCRnx 1 OCRnx 2 clkI O clkTn clkI O 8 OCFnx OCRnx TCNTn CTC TOP TOP 1 TOP B...

Page 157: ...tive This is particularly important if any of the Output Compare2 interrupt is used to wake up the device since the Output Compare function is disabled during writing to OCR2x or TCNT2 If the write cycle is not finished and the MCU enters sleep mode before the corresponding OCR2xUB bit returns to zero the device will never receive a compare match interrupt and the MCU will not wake up If Timer Cou...

Page 158: ...TOSC clock after waking up from Power save mode is essentially unpredictable as it depends on the wake up time The recommended procedure for reading TCNT2 is thus as follows a Write any value to either of the registers OCR2x or TCCR2x b Wait for the corresponding Update Busy Flag to be cleared c Read TCNT2 During asynchronous operation the synchronization of the Interrupt Flags for the asynchronou...

Page 159: ...s an independent clock source for Timer Counter2 The Oscillator is optimized for use with a 32 768kHz crystal For Timer Counter2 the possible prescaled selections are clkT2S 8 clkT2S 32 clkT2S 64 clkT2S 128 clkT2S 256 and clkT2S 1024 Additionally clkT2S as well as 0 stop may be selected Setting the PSRASY bit in GTCCR resets the prescaler This allows the user to operate with a predictable prescale...

Page 160: ...nctionality when the WGM21 0 bits are set to fast PWM mode Note 1 A special case occurs when OCR2A equals TOP and COM2A1 is set In this case the Com pare Match is ignored but the set or clear is done at BOTTOM See Fast PWM Mode on page 152 for more details Bit 7 6 5 4 3 2 1 0 0xB0 COM2A1 COM2A0 COM2B1 COM2B0 WGM21 WGM20 TCCR2A Read Write R W R W R W R W R R R W R W Initial Value 0 0 0 0 0 0 0 0 Ta...

Page 161: ...M2B1 0 bit functionality when the WGM22 0 bits are set to a normal or CTC mode non PWM Table 18 6 shows the COM2B1 0 bit functionality when the WGM22 0 bits are set to fast PWM mode Table 18 4 Compare Output Mode Phase Correct PWM Mode 1 COM2A1 COM2A0 Description 0 0 Normal port operation OC2A disconnected 0 1 WGM22 0 Normal Port Operation OC2A Disconnected WGM22 1 Toggle OC2A on Compare Match 1 0...

Page 162: ...ce for maximum TOP counter value and what type of wave form generation to be used see Table 18 8 Modes of operation supported by the Timer Counter unit are Normal mode counter Clear Timer on Compare Match CTC mode and two types of Pulse Width Modulation PWM modes see Modes of Operation on page 151 Notes 1 MAX 0xFF 2 BOTTOM 0x00 Table 18 7 Compare Output Mode Phase Correct PWM Mode 1 COM2B1 COM2B0 ...

Page 163: ...WM mode However for ensuring compatibility with future devices this bit must be set to zero when TCCR2B is written when operating in PWM mode When writing a logical one to the FOC2B bit an immediate Compare Match is forced on the Waveform Generation unit The OC2B output is changed according to its COM2B1 0 bits setting Note that the FOC2B bit is implemented as a strobe Therefore it is the value pr...

Page 164: ...to generate an Output Compare interrupt or to generate a waveform output on the OC2A pin 18 11 5 OCR2B Output Compare Register B The Output Compare Register B contains an 8 bit value that is continuously compared with the counter value TCNT2 A match can be used to generate an Output Compare interrupt or to generate a waveform output on the OC2B pin Table 18 9 Clock Select Bit Description CS22 CS21...

Page 165: ...een the Timer Counter2 and the data in OCR2B Output Compare Register2 OCF2B is cleared by hardware when executing the corresponding interrupt handling vector Alternatively OCF2B is cleared by writing a logic one to the flag When the I bit in SREG OCIE2B Timer Counter2 Compare match Interrupt Enable and OCF2B are set one the Timer Counter2 Compare match Interrupt is executed Bit 1 OCF2A Output Comp...

Page 166: ...ten this bit becomes set When OCR2A has been updated from the temporary storage register this bit is cleared by hard ware A logical zero in this bit indicates that OCR2A is ready to be updated with a new value Bit 2 OCR2BUB Output Compare Register2 Update Busy When Timer Counter2 operates asynchronously and OCR2B is written this bit becomes set When OCR2B has been updated from the temporary storag...

Page 167: ...n this bit is one the Timer Counter2 prescaler will be reset This bit is normally cleared immediately by hardware If the bit is written when Timer Counter2 is operating in asynchronous mode the bit will remain one until the prescaler has been reset The bit will not be cleared by hardware if the TSM bit is set Refer to the description of the Bit 7 TSM Timer Counter Syn chronization Mode on page 145...

Page 168: ...pt Flag Write Collision Flag Protection Wake up from Idle Mode Double Speed CK 2 Master SPI Mode 19 2 Overview The Serial Peripheral Interface SPI allows high speed synchronous data transfer between the ATmega48A PA 88A PA 168A PA 328 P and peripheral devices or between several AVR devices The USART can also be used in Master SPI mode see USART in SPI Mode on page 206 The PRSPI bit in Minimizing P...

Page 169: ... of the SS line This must be handled by user software before communication can start When this is done writing a byte to the SPI Data Register starts the SPI clock generator and the hardware shifts the eight bits into the Slave After shifting one byte the SPI clock generator stops setting the end of Transmission Flag SPIF If the SPI Interrupt Enable bit SPIE in the SPCR Register is set an interrup...

Page 170: ... high periods should be Low periods Longer than 2 CPU clock cycles High periods Longer than 2 CPU clock cycles When the SPI is enabled the data direction of the MOSI MISO SCK and SS pins is overridden according to Table 19 1 on page 170 For more details on automatic port overrides refer to Alternate Port Functions on page 82 Note See Alternate Functions of Port B on page 84 for a detailed descript...

Page 171: ... MSTR 1 SPR0 out SPCR r17 ret SPI_MasterTransmit Start transmission of data r16 out SPDR r16 Wait_Transmit Wait for transmission complete in r16 SPSR sbrsr16 SPIF rjmp Wait_Transmit ret C Code Example 1 void SPI_MasterInit void Set MOSI and SCK output all others input DDR_SPI 1 DD_MOSI 1 DD_SCK Enable SPI Master set clock rate fck 16 SPCR 1 SPE 1 MSTR 1 SPR0 void SPI_MasterTransmit char cData Star...

Page 172: ...put all others input ldi r17 1 DD_MISO out DDR_SPI r17 Enable SPI ldi r17 1 SPE out SPCR r17 ret SPI_SlaveReceive Wait for reception complete in r16 SPSR sbrs r16 SPIF rjmp SPI_SlaveReceive Read received data and return in r16 SPDR ret C Code Example 1 void SPI_SlaveInit void Set MISO output all others input DDR_SPI 1 DD_MISO Enable SPI SPCR 1 SPE char SPI_SlaveReceive void Wait for reception comp...

Page 173: ...ut the SPI system interprets this as another master selecting the SPI as a slave and starting to send data to it To avoid bus contention the SPI system takes the following actions 1 The MSTR bit in SPCR is cleared and the SPI system becomes a Slave As a result of the SPI becoming a Slave the MOSI and SCK pins become inputs 2 The SPIF Flag in SPSR is set and if the SPI interrupt is enabled and the ...

Page 174: ... I MOSI MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SCK CPOL 1 mode 2 SS MSB LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 MSB first DORD 0 LSB first DORD 1 SCK CPOL 0 mode 1 SAMPLE I MOSI MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SCK CPOL 1 mode 3 SS MSB LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB MSB first DORD 0 LSB first DORD 1 ...

Page 175: ...nput and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR will become set The user will then have to set MSTR to re enable SPI Mas ter mode Bit 3 CPOL Clock Polarity When this bit is written to one SCK is high when idle When CPOL is written to zero SCK is low when idle Refer to Figure 19 3 and Figure 19 4 for an example The CPOL functionality is sum marized below Bit 2 CPHA Cl...

Page 176: ...egister SPDR is written during a data transfer The WCOL bit and the SPIF bit are cleared by first reading the SPI Status Register with WCOL set and then accessing the SPI Data Register Bit 5 1 Reserved These bits are reserved bits in the ATmega48A PA 88A PA 168A PA 328 P and will always read as zero Bit 0 SPI2X Double SPI Speed Bit When this bit is written logic one the SPI speed SCK Frequency wil...

Page 177: ...er used for data transfer between the Register File and the SPI Shift Register Writing to the register initiates data transmission Reading the regis ter causes the Shift Register Receive buffer to be read Bit 7 6 5 4 3 2 1 0 0x2E 0x4E MSB LSB SPDR Read Write R W R W R W R W R W R W R W R W Initial Value X X X X X X X X Undefined ...

Page 178: ...a logical zero to it A simplified block diagram of the USART Transmitter is shown in Figure 20 1 on page 179 CPU accessible I O Registers and I O pins are shown in bold The dashed boxes in the block diagram separate the three main parts of the USART listed from the top Clock Generator Transmitter and Receiver Control Registers are shared by all units The Clock Generation logic consists of synchron...

Page 179: ...ects between asynchronous and synchronous operation Double Speed asynchronous mode only is controlled by the U2Xn found in the UCSRnA Register When using synchronous mode UMSELn 1 the Data Direction Register for the XCKn pin DDR_XCKn controls whether the clock source is internal Master mode or external Slave mode The XCKn pin is only active when using synchronous mode PARITY GENERATOR UBRRn H L UD...

Page 180: ...e Register UBRRn and the down counter connected to it function as a programmable prescaler or baud rate generator The down counter running at system clock fosc is loaded with the UBRRn value each time the counter has counted down to zero or when the UBRRnL Register is written A clock is generated each time the counter reaches zero This clock is the baud rate generator clock output fosc UBRRn 1 The...

Page 181: ...or the asynchronous operation Set this bit to zero when using synchronous operation Setting this bit will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication Note however that the Receiver will in this case only use half the number of samples reduced from 16 to 8 for data sampling and clock recovery and therefore a more acc...

Page 182: ...SELn 1 the XCKn pin will be used as either clock input Slave or clock output Master The dependency between the clock edges and data sampling or data change is the same The basic principle is that data input on RxDn is sampled at the opposite XCKn clock edge of the edge the data output TxDn is changed Figure 20 3 Synchronous Mode XCKn Timing The UCPOLn bit UCRSC selects which XCKn clock edge is use...

Page 183: ...and Transmitter use the same setting Note that changing the setting of any of these bits will corrupt all ongoing communication for both the Receiver and Transmitter The USART Character SiZe UCSZn2 0 bits select the number of data bits in the frame The USART Parity mode UPMn1 0 bits enable and set the type of parity bit The selection between one or two stop bits is done by the USART Stop Bit Selec...

Page 184: ...there are no ongoing transmissions during the period the registers are changed The TXCn Flag can be used to check that the Transmitter has completed all transfers and the RXC Flag can be used to check that there are no unread data in the receive buffer Note that the TXCn Flag must be cleared before each transmission before UDRn is written if it is used for this purpose The following simple USART i...

Page 185: ...tter is enabled the normal port operation of the TxDn pin is overrid den by the USART and given the function as the Transmitter s serial output The baud rate mode of operation and frame format must be set up once before doing any transmissions If syn Assembly Code Example 1 USART_Init Set baud rate out UBRRnH r17 out UBRRnL r16 Enable receiver and transmitter ldi r16 1 RXENn 1 TXENn out UCSRnB r16...

Page 186: ...than eight bits the most sig nificant bits written to the UDRn are ignored The USART has to be initialized before the function can be used For the assembly code the data to be sent is assumed to be stored in Register R16 Note 1 See About Code Examples on page 8 The function simply waits for the transmit buffer to be empty by checking the UDREn Flag before loading it with new data to be transmitted...

Page 187: ...hen the transmit buffer contains data to be transmitted that has not yet been moved into the Shift Register For compat ibility with future devices always write this bit to zero when writing the UCSRnA Register When the Data Register Empty Interrupt Enable UDRIEn bit in UCSRnB is written to one the USART Data Register Empty Interrupt will be executed as long as UDREn is set provided that global int...

Page 188: ...ter setting the TXEN to zero will not become effective until ongo ing and pending transmissions are completed i e when the Transmit Shift Register and Transmit Buffer Register do not contain data to be transmitted When disabled the Transmitter will no longer override the TxDn pin 20 7 Data Reception The USART Receiver The USART Receiver is enabled by writing the Receive Enable RXENn bit in the UCS...

Page 189: ... in UCSRnB before reading the low bits from the UDRn This rule applies to the FEn DORn and UPEn Status Flags as well Read status from UCSRnA then data from UDRn Reading the UDRn I O location will change the state of the receive buffer FIFO and consequently the TXB8n FEn DORn and UPEn bits which all are stored in the FIFO will change The following code example shows a simple USART receive function ...

Page 190: ...USART_Receive Get status and 9th bit then data from buffer in r18 UCSRnA in r17 UCSRnB in r16 UDRn If error return 1 andi r18 1 FEn 1 DORn 1 UPEn breq USART_ReceiveNoError ldi r17 HIGH 1 ldi r16 LOW 1 USART_ReceiveNoError Filter the 9th bit then return lsr r17 andi r17 0x01 ret C Code Example 1 unsigned int USART_Receive void unsigned char status resh resl Wait for data to be received while UCSRnA...

Page 191: ...a write to the flag location However all flags must be set to zero when the UCSRnA is written for upward compatibility of future USART implementations None of the Error Flags can generate interrupts The Frame Error FEn Flag indicates the state of the first stop bit of the next readable frame stored in the receive buffer The FEn Flag is zero when the stop bit was correctly read as one and the FEn F...

Page 192: ...i e the buffer will be emptied of its contents Unread data will be lost If the buffer has to be flushed during normal operation due to for instance an error condition read the UDRn I O location until the RXCn Flag is cleared The following code example shows how to flush the receive buffer Note 1 See About Code Examples on page 8 For I O Registers located in extended I O map IN OUT SBIS SBIC CBI an...

Page 193: ...ext high to low transition If however a valid start bit is detected the clock recov ery logic is synchronized and the data recovery can begin The synchronization process is repeated for each start bit 20 8 2 Asynchronous Data Recovery When the receiver clock is synchronized to the start bit the data recovery can begin The data recovery unit uses a state machine that has 16 states for each bit in N...

Page 194: ...nge The operational range of the Receiver is dependent on the mismatch between the received bit rate and the internally generated baud rate If the Transmitter is sending frames at too fast or too slow bit rates or the internally generated baud rate of the Receiver does not have a similar see Table 20 2 on page 195 base frequency the Receiver will not be able to synchronize the frames to the start ...

Page 195: ...low error can be used if possible 20 9 Multi processor Communication Mode Setting the Multi processor Communication mode MPCMn bit in UCSRnA enables a filtering function of incoming frames received by the USART Receiver Frames that do not contain address information will be ignored and not put into the receive buffer This effectively reduces the number of incoming frames that has to be handled by ...

Page 196: ...CSRnA is set 2 The Master MCU sends an address frame and all slaves receive and read this frame In the Slave MCUs the RXCn Flag in UCSRnA will be set as normal 3 Each Slave MCU reads the UDRn Register and determines if it has been selected If so it clears the MPCMn bit in UCSRnA otherwise it waits for the next address byte and keeps the MPCMn setting 4 The addressed MCU will receive all data frame...

Page 197: ...osc 1 0000MHz fosc 1 8432MHz fosc 2 0000MHz U2Xn 0 U2Xn 1 U2Xn 0 U2Xn 1 U2Xn 0 U2Xn 1 UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error 2400 25 0 2 51 0 2 47 0 0 95 0 0 51 0 2 103 0 2 4800 12 0 2 25 0 2 23 0 0 47 0 0 25 0 2 51 0 2 9600 6 7 0 12 0 2 11 0 0 23 0 0 12 0 2 25 0 2 14 4k 3 8 5 8 3 5 7 0 0 15 0 0 8 3 5 16 2 1 19 2k 2 8 5 6 7 0 5 0 0 11 0 0 6 7 0 12 0 2 28 8k 1 8 5 3...

Page 198: ... 2 103 0 2 95 0 0 191 0 0 9600 23 0 0 47 0 0 25 0 2 51 0 2 47 0 0 95 0 0 14 4k 15 0 0 31 0 0 16 2 1 34 0 8 31 0 0 63 0 0 19 2k 11 0 0 23 0 0 12 0 2 25 0 2 23 0 0 47 0 0 28 8k 7 0 0 15 0 0 8 3 5 16 2 1 15 0 0 31 0 0 38 4k 5 0 0 11 0 0 6 7 0 12 0 2 11 0 0 23 0 0 57 6k 3 0 0 7 0 0 3 8 5 8 3 5 7 0 0 15 0 0 76 8k 2 0 0 5 0 0 2 8 5 6 7 0 5 0 0 11 0 0 115 2k 1 0 0 3 0 0 1 8 5 3 8 5 3 0 0 7 0 0 230 4k 0 0...

Page 199: ...0 0 383 0 0 9600 51 0 2 103 0 2 71 0 0 143 0 0 95 0 0 191 0 0 14 4k 34 0 8 68 0 6 47 0 0 95 0 0 63 0 0 127 0 0 19 2k 25 0 2 51 0 2 35 0 0 71 0 0 47 0 0 95 0 0 28 8k 16 2 1 34 0 8 23 0 0 47 0 0 31 0 0 63 0 0 38 4k 12 0 2 25 0 2 17 0 0 35 0 0 23 0 0 47 0 0 57 6k 8 3 5 16 2 1 11 0 0 23 0 0 15 0 0 31 0 0 76 8k 6 7 0 12 0 2 8 0 0 17 0 0 11 0 0 23 0 0 115 2k 3 8 5 8 3 5 5 0 0 11 0 0 7 0 0 15 0 0 230 4k ...

Page 200: ...59 0 2 520 0 0 9600 103 0 2 207 0 2 119 0 0 239 0 0 129 0 2 259 0 2 14 4k 68 0 6 138 0 1 79 0 0 159 0 0 86 0 2 173 0 2 19 2k 51 0 2 103 0 2 59 0 0 119 0 0 64 0 2 129 0 2 28 8k 34 0 8 68 0 6 39 0 0 79 0 0 42 0 9 86 0 2 38 4k 25 0 2 51 0 2 29 0 0 59 0 0 32 1 4 64 0 2 57 6k 16 2 1 34 0 8 19 0 0 39 0 0 21 1 4 42 0 9 76 8k 12 0 2 25 0 2 14 0 0 29 0 0 15 1 7 32 1 4 115 2k 8 3 5 16 2 1 9 0 0 19 0 0 10 1 ...

Page 201: ... using bit test instructions SBIC and SBIS since these also will change the state of the FIFO 20 11 2 UCSRnA USART Control and Status Register n A Bit 7 RXCn USART Receive Complete This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty i e does not contain any unread data If the Receiver is disabled the receive buffer will be flushed and ...

Page 202: ...Speed This bit only has effect for the asynchronous operation Write this bit to zero when using syn chronous operation Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively dou bling the transfer rate for asynchronous communication Bit 0 MPCMn Multi processor Communication Mode This bit enables the Multi processor Communication mode When the MPCMn bit is...

Page 203: ...ans mitted When disabled the Transmitter will no longer override the TxDn port Bit 2 UCSZn2 Character Size n The UCSZn2 bits combined with the UCSZn1 0 bit in UCSRnC sets the number of data bits Character SiZe in a frame the Receiver and Transmitter use Bit 1 RXB8n Receive Data Bit 8 n RXB8n is the ninth data bit of the received character when operating with serial frames with nine data bits Must ...

Page 204: ... UCSZn1 0 Character Size The UCSZn1 0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits Character SiZe in a frame the Receiver and Transmitter use Bit 0 UCPOLn Clock Polarity This bit is used for synchronous mode only Write this bit to zero when asynchronous mode is used The UCPOLn bit sets the relationship between data output change and data input sample and the synchronous...

Page 205: ...nL contains the eight least significant bits of the USART baud rate Ongoing transmissions by the Transmitter and Receiver will be corrupted if the baud rate is changed Writing UBRRnL will trigger an immediate update of the baud rate prescaler Table 20 11 UCPOLn Bit Settings UCPOLn Transmitted Data Changed Output of TxDn Pin Received Data Sampled Input on RxDn Pin 0 Rising XCKn Edge Falling XCKn Ed...

Page 206: ...cker the data and clock recovery logic and the RX and TX control logic is disabled The USART RX and TX control logic is replaced by a common SPI transfer control logic However the pin control logic and interrupt generation logic is identical in both modes of operation The I O register locations are the same in both modes However some of the functionality of the control registers changes when using...

Page 207: ...d in on opposite edges of the XCKn signal ensuring sufficient time for data signals to stabilize The UCPOLn and UCPHAn function ality is summarized in Table 21 2 Note that changing the setting of any of these bits will corrupt all ongoing communication for both the Receiver and Transmitter Table 21 1 Equations for Calculating Baud Rate Register Setting Operating Mode Equation for Calculating Baud ...

Page 208: ...mmunication can take place The initialization process normally consists of setting the baud rate setting master mode of operation by setting DDR_XCKn to one setting frame format and enabling the Transmitter and the Receiver Only the transmitter can operate independently For interrupt driven USART opera tion the Global Interrupt Flag should be cleared and thus interrupts globally disabled when doin...

Page 209: ...ly Code Example 1 USART_Init clr r18 out UBRRnH r18 out UBRRnL r18 Setting the XCKn port pin as output enables master mode sbi XCKn_DDR XCKn Set MSPI mode of operation and SPI data mode 0 ldi r18 1 UMSELn1 1 UMSELn0 0 UCPHAn 0 UCPOLn out UCSRnC r18 Enable receiver and transmitter ldi r18 1 RXENn 1 TXENn out UCSRnB r18 Set baud rate IMPORTANT The Baud Rate must be set after the transmitter is enabl...

Page 210: ...new frame Note To keep the input buffer in sync with the number of data bytes transmitted the UDRn register must be read once for each byte transmitted The input buffer operation is identical to normal USART mode i e if an overflow occurs the character last received will be lost not the first data in the buf fer This means that if four bytes are transferred byte 1 first then byte 2 3 and 4 and the...

Page 211: ...in USART in MSPIM mode is identical in function to the normal USART operation Assembly Code Example 1 USART_MSPIM_Transfer Wait for empty transmit buffer in r16 UCSRnA sbrs r16 UDREn rjmp USART_MSPIM_Transfer Put data r16 into buffer sends the data out UDRn r16 Wait for data to be received USART_MSPIM_Wait_RXCn in r16 UCSRnA sbrs r16 RXCn rjmp USART_MSPIM_Wait_RXCn Get and return received data fro...

Page 212: ...in MSPIM mode the following features differ between the two modules The USART in MSPIM mode includes double buffering of the transmitter The SPI has no buffer The USART in MSPIM mode receiver includes an additional buffer level The SPI WCOL Write Collision bit is not included in USART in MSPIM mode The SPI double speed mode SPI2X bit is not included However the same effect is achieved by setting U...

Page 213: ...t complete interrupt is executed or it can be cleared by writing a one to its bit location The TXCn Flag can generate a Transmit Complete interrupt see description of the TXCIEn bit Bit 5 UDREn USART Data Register Empty The UDREn Flag indicates if the transmit buffer UDRn is ready to receive new data If UDREn is one the buffer is empty and therefore ready to be written The UDREn Flag can generate ...

Page 214: ...les the USART Transmitter The Transmitter will override normal port operation for the TxDn pin when enabled The disabling of the Transmitter writing TXENn to zero will not become effective until ongoing and pending transmissions are completed i e when the Transmit Shift Register and Transmit Buffer Register do not contain data to be trans mitted When disabled the Transmitter will no longer overrid...

Page 215: ...An Clock Phase The UCPHAn bit setting determine if data is sampled on the leasing edge first or tailing last edge of XCKn Refer to the SPI Data Modes and Timing section page 4 for details Bit 0 UCPOLn Clock Polarity The UCPOLn bit sets the polarity of the XCKn clock The combination of the UCPOLn and UCPHAn bit settings determine the timing of the data transfer Refer to the SPI Data Modes and Timin...

Page 216: ... Address Recognition Causes Wake up When AVR is in Sleep Mode Compatible with Philips I2 C protocol 22 2 2 wire Serial Interface Bus Definition The 2 wire Serial Interface TWI is ideally suited for typical microcontroller applications The TWI protocol allows the systems designer to interconnect up to 128 different devices using only two bi directional bus lines one for clock SCL and one for data S...

Page 217: ...all TWI devices tri state their outputs allowing the pull up resistors to pull the line high Note that all AVR devices connected to the TWI bus must be powered in order to allow any bus operation The number of devices that can be connected to the bus is only limited by the bus capacitance limit of 400 pF and the 7 bit slave address space A detailed specification of the electrical char acteristics ...

Page 218: ...on the bus is considered busy and no other master should try to seize control of the bus A special case occurs when a new START condition is issued between a START and STOP condition This is referred to as a REPEATED START condition and is used when the Master wishes to initiate a new transfer without relin quishing control of the bus After a REPEATED START the bus is considered busy until the nex...

Page 219: ...to transmit the same message to several slaves in the system When the general call address followed by a Write bit is transmitted on the bus all slaves set up to acknowledge the general call will pull the SDA line low in the ack cycle The following data packets will then be received by all the slaves that acknowledged the general call Note that transmitting the general call address followed by a R...

Page 220: ...n the SLA R W and the STOP condition depending on the software protocol imple mented by the application software Figure 22 6 Typical Data Transmission 22 4 Multi master Bus Systems Arbitration and Synchronization The TWI protocol allows bus systems with several masters Special concerns have been taken in order to ensure that transmissions will proceed as normal even if two or more masters initiate...

Page 221: ...r SCL high and low time out periods when the combined SCL line goes high or low respectively Figure 22 7 SCL Synchronization Between Multiple Masters Arbitration is carried out by all masters continuously monitoring the SDA line after outputting data If the value read from the SDA line does not match the value the Master had output it has lost the arbitration Note that a Master can only lose arbit...

Page 222: ...s the user software s responsibility to ensure that these illegal arbitration conditions never occur This implies that in multi master systems all data transfers must use the same composi tion of SLA R W and data packets In other words All transmissions must contain the same number of data packets otherwise the result of the arbitration is undefined SDA from Master A SDA from Master B SDA Line Syn...

Page 223: ...I O Port section The internal pull ups can in some systems eliminate the need for external ones 22 5 2 Bit Rate Generator Unit This unit controls the period of SCL when operating in a Master mode The SCL period is con trolled by settings in the TWI Bit Rate Register TWBR and the Prescaler bits in the TWI Status Register TWSR Slave operation does not depend on Bit Rate or Prescaler settings but the...

Page 224: ... the transmission trying to determine if arbitration is in process If the TWI has lost an arbitration the Control Unit is informed Correct action can then be taken and appropriate status codes generated 22 5 4 Address Match Unit The Address Match unit checks if received address bytes match the seven bit address in the TWI Address Register TWAR If the TWI General Call Recognition Enable TWGCE bit i...

Page 225: ...nipulating the TWCR and TWDR Registers Figure 22 10 is a simple example of how the application can interface to the TWI hardware In this example a Master wishes to transmit a single data byte to a Slave This description is quite abstract a more detailed explanation follows later in this section A simple code example imple menting the desired behavior is also presented Figure 22 10 Interfacing the ...

Page 226: ...cates otherwise the application software might take some special action like calling an error routine Assuming that the status code is as expected the application must load a data packet into TWDR Subsequently a specific value must be written to TWCR instructing the TWI hardware to transmit the data packet present in TWDR Which value to write is described later on However it is important that the ...

Page 227: ...er all TWI Register updates and other pending application software tasks have been completed TWCR is written When writing TWCR the TWINT bit should be set Writing a one to TWINT clears the flag The TWI will then commence executing whatever operation was specified by the TWCR setting In the following an assembly and C implementation of the example is given Note that the code below assumes that seve...

Page 228: ... while TWCR 1 TWINT Wait for TWINT Flag set This indicates that the SLA W has been transmitted and ACK NACK has been received 5 in r16 TWSR andi r16 0xF8 cpi r16 MT_SLA_ACK brne ERROR if TWSR 0xF8 MT_SLA_ACK ERROR Check value of TWI Status Register Mask prescaler bits If status different from MT_SLA_ACK go to ERROR ldi r16 DATA out TWDR r16 ldi r16 1 TWINT 1 TWEN out TWCR r16 TWDR DATA TWCR 1 TWIN...

Page 229: ...n SLA Slave Address In Figure 22 12 to Figure 22 18 circles are used to indicate that the TWINT Flag is set The numbers in the circles show the status code held in TWSR with the prescaler bits masked to zero At these points actions must be taken by the application to continue or complete the TWI transfer The TWI transfer is suspended until the TWINT Flag is cleared by software When the TWINT Flag ...

Page 230: ...8 The appropriate action to be taken for each of these status codes is detailed in Table 22 2 When SLA W has been successfully transmitted a data packet should be transmitted This is done by writing the data byte to TWDR TWDR must only be written when TWINT is high If not the access will be discarded and the Write Collision bit TWWC will be set in the TWCR Regis ter After updating TWDR the TWINT b...

Page 231: ...e transmitted and TWSTO Flag will be reset 0x20 SLA W has been transmitted NOT ACK has been received Load data byte or No TWDR action or No TWDR action or No TWDR action 0 1 0 1 0 0 1 1 1 1 1 1 X X X X Data byte will be transmitted and ACK or NOT ACK will be received Repeated START will be transmitted STOP condition will be transmitted and TWSTO Flag will be reset STOP condition followed by a STAR...

Page 232: ...ssume that the prescaler bits are zero or are masked to zero S SLA W A DATA A P 08 18 28 R SLA W 10 A P 20 P 30 A or A 38 A Other master continues A or A 38 Other master continues R A 68 Other master continues 78 B0 To corresponding states in slave mode MT MR Successfull transmission to a slave receiver Next transfer started with a repeated start condition Not acknowledge received after the slave ...

Page 233: ...ble status codes in Master mode are 0x38 0x40 or 0x48 The appropriate action to be taken for each of these status codes is detailed in Table 22 3 Received data can be read from the TWDR Register when the TWINT Flag is set high by hardware This scheme is repeated until the last byte has been received After the last byte has been received the MR should inform the ST by sending a NACK after the last ...

Page 234: ...e entered A START condition will be transmitted when the bus becomes free 0x40 SLA R has been transmitted ACK has been received No TWDR action or No TWDR action 0 0 0 0 1 1 0 1 Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned 0x48 SLA R has been transmitted NOT ACK has been received No TWDR action or No TWDR action or No TWDR action 1 0 1 ...

Page 235: ...ther master continues W A 68 Other master continues 78 B0 To corresponding states in slave mode MR MT Successfull reception from a slave receiver Next transfer started with a repeated start condition Not acknowledge received after the slave address Arbitration lost in slave address or data byte Arbitration lost and addressed as slave DATA A n From master to slave From slave to master Any number of...

Page 236: ...de see states 0x68 and 0x78 If the TWEA bit is reset during a transfer the TWI will return a Not Acknowledge 1 to SDA after the next received data byte This can be used to indicate that the Slave is not able to receive any more bytes While TWEA is zero the TWI does not acknowledge its own slave address However the 2 wire Serial Bus is still monitored and address recognition may resume at any time ...

Page 237: ... SLA or GCA Switched to the not addressed Slave mode own SLA will be recognized GCA will be recognized if TWGCE 1 Switched to the not addressed Slave mode no recognition of own SLA or GCA a START condition will be transmitted when the bus becomes free Switched to the not addressed Slave mode own SLA will be recognized GCA will be recognized if TWGCE 1 a START condition will be transmitted when the...

Page 238: ...re acknowledged Last data byte received is not acknowledged Arbitration lost as master and addressed as slave Reception of the general call address and one or more data bytes Last data byte received is not acknowledged n From master to slave From slave to master Any number of data bytes and their associated acknowledge bits This number contained in TWSR corresponds to a defined state of the 2 Wire...

Page 239: ...ether the Master Receiver transmits a NACK or ACK after the final byte The TWI is switched to the not addressed Slave mode and will ignore the Master if it continues the transfer Thus the Master Receiver receives all 1 as serial data State 0xC8 is entered if the Master demands additional data bytes by transmitting ACK even though the Slave has transmitted the last byte TWEA zero and expect ing NAC...

Page 240: ...een transmitted NOT ACK has been received No TWDR action or No TWDR action or No TWDR action or No TWDR action 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 Switched to the not addressed Slave mode no recognition of own SLA or GCA Switched to the not addressed Slave mode own SLA will be recognized GCA will be recognized if TWGCE 1 Switched to the not addressed Slave mode no recognition of own SLA or GCA a START...

Page 241: ... complete the desired action Consider for example reading data from a serial EEPROM Typically such a transfer involves the following steps 1 The transfer must be initiated 2 The EEPROM must be instructed what location should be read 3 The reading must be performed 4 The transfer must be finished S SLA R A DATA A A8 B8 A B0 Reception of the own slave address and one or more data bytes Last data byt...

Page 242: ... by one or more of them The TWI standard ensures that such situations are handled in such a way that one of the masters will be allowed to proceed with the transfer and that no data will be lost in the process An example of an arbitration situation is depicted below where two masters are trying to transmit data to a Slave Receiver Figure 22 20 An Arbitration Example Several different scenarios may...

Page 243: ... 223 for calculating bit rates 22 9 2 TWCR TWI Control Register The TWCR is used to control the operation of the TWI It is used to enable the TWI to initiate a Master access by applying a START condition to the bus to generate a Receiver acknowledge to generate a stop condition and to control halting of the bus while the data to be written to the bus are written to the TWDR It also indicates a wri...

Page 244: ...ion Bit The application writes the TWSTA bit to one when it desires to become a Master on the 2 wire Serial Bus The TWI hardware checks if the bus is available and generates a START condition on the bus if it is free However if the bus is not free the TWI waits until a STOP condition is detected and then generates a new START condition to claim the bus Master status TWSTA must be cleared by softwa...

Page 245: ...ates see Bit Rate Generator Unit on page 223 The value of TWPS1 0 is used in the equation 22 9 4 TWDR TWI Data Register In Transmit mode TWDR contains the next byte to be transmitted In Receive mode the TWDR contains the last byte received It is writable while the TWI is not in the process of shifting a byte This occurs when the TWI Interrupt Flag TWINT is set by hardware Note that the Data Regis ...

Page 246: ...ooks for the slave address or general call address if enabled in the received serial address If a match is found an interrupt request is generated Bits 7 1 TWA TWI Slave Address Register These seven bits constitute the slave address of the TWI unit Bit 0 TWGCE TWI General Call Recognition Enable Bit If set this bit enables the recognition of a General Call given over the 2 wire Serial Bus 22 9 6 T...

Page 247: ... Figure 22 22 TWI Address Match Logic Block Diagram Bit 0 Reserved This bit is an unused bit in the ATmega48A PA 88A PA 168A PA 328 P and will always read as zero Address Match Address Bit Comparator 0 Address Bit Comparator 6 1 TWAR0 TWAMR0 Address Bit 0 ...

Page 248: ...umption on page 43 must be disabled by writing a logical zero to be able to use the ADC input MUX Figure 23 1 Analog Comparator Block Diagram 2 Notes 1 See Table 23 1 on page 249 2 Refer to Figure 1 1 on page 2 and Table 14 9 on page 90 for Analog Comparator pin placement 23 2 Analog Comparator Multiplexed Input It is possible to select any of the ADC7 0 pins to replace the negative input to the A...

Page 249: ...in Active and Idle mode When changing the ACD bit the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR Otherwise an interrupt can occur when the bit is changed Bit 6 ACBG Analog Comparator Bandgap Select When this bit is set a fixed bandgap reference voltage replaces the positive input to the Analog Comparator When this bit is cleared AIN0 is applied to the positive in...

Page 250: ...log Comparator Input Capture Enable When written logic one this bit enables the input capture function in Timer Counter1 to be trig gered by the Analog Comparator The comparator output is in this case directly connected to the input capture front end logic making the comparator utilize the noise canceler and edge select features of the Timer Counter1 Input Capture interrupt When written logic zero...

Page 251: ...hen this bit is written logic one the digital input buffer on the AIN1 0 pin is disabled The corre sponding PIN Register bit will always read as zero when this bit is set When an analog signal is applied to the AIN1 0 pin and the digital input from this pin is not needed this bit should be writ ten logic one to reduce power consumption in the digital input buffer Bit 7 6 5 4 3 2 1 0 0x7F AIN1D AIN...

Page 252: ...and Hold circuit which ensures that the input voltage to the ADC is held at a constant level during conversion A block diagram of the ADC is shown in Figure 24 1 on page 253 The ADC has a separate analog supply voltage pin AVCC AVCC must not differ more than 0 3V from VCC See the paragraph ADC Noise Canceler on page 258 on how to connect this pin Internal reference voltages of nominally 1 1V or AV...

Page 253: ...nted right adjusted but can optionally be presented left adjusted by setting the ADLAR bit in ADMUX If the result is left adjusted and no more than 8 bit precision is required it is sufficient to read ADCH Otherwise ADCL must be read first then ADCH to ensure that the content of the Data Registers belongs to the same conversion Once ADCL is read ADC access to Data Registers is blocked This means t...

Page 254: ...ger Select bits ADTS in ADCSRB See description of the ADTS bits for a list of the trigger sources When a positive edge occurs on the selected trigger signal the ADC prescaler is reset and a conversion is started This provides a method of starting con versions at fixed intervals If the trigger signal still is set when the conversion completes a new conversion will not be started If another positive...

Page 255: ...ts at the following rising edge of the ADC clock cycle A normal conversion takes 13 ADC clock cycles The first conversion after the ADC is switched on ADEN in ADCSRA is set takes 25 ADC clock cycles in order to initialize the analog circuitry When the bandgap reference voltage is used as input to the ADC it will take a certain time for the voltage to stabilize If not stabilized the first value rea...

Page 256: ...k ADSC Sample Hold ADIF ADCH ADCL Cycle Number ADEN 1 2 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 First Conversion Next Conversion 3 MUX and REFS Update MUX and REFS Update Conversion Complete 1 2 3 4 5 6 7 8 9 10 11 12 13 Sign and MSB of Result LSB of Result ADC Clock ADSC ADIF ADCH ADCL Cycle Number 1 2 One Conversion Next Conversion 3 Sample Hold MUX and REFS Update Conversion Complete MUX ...

Page 257: ...Auto Triggering is used the exact time of the triggering event can be indeterministic Special care must be taken when updating the ADMUX Register in order to control which conversion will be affected by the new settings If both ADATE and ADEN is written to one an interrupt event can occur at any time If the ADMUX Register is changed in this period the user cannot tell if the next conversion is bas...

Page 258: ...mpedance voltmeter Note that VREF is a high impedance source and only a capacitive load should be connected in a system If the user has a fixed voltage source connected to the AREF pin the user may not use the other reference voltage options in the application as they will be shorted to the external voltage If no external voltage is applied to the AREF pin the user may switch between AVCC and 1 1V...

Page 259: ...nents higher than the Nyquist frequency fADC 2 should not be present for either kind of channels to avoid distortion from unpredictable signal convolution The user is advised to remove high frequency components with a low pass filter before applying the signals as inputs to the ADC Figure 24 8 Analog Input Circuitry 24 6 2 Analog Noise Canceling Techniques Digital circuitry inside and outside the ...

Page 260: ...ts a voltage linearly between GND and VREF in 2n steps LSBs The lowest code is read as 0 and the highest code is read as 2n 1 Several parameters describe the deviation from the ideal behavior Offset The deviation of the first transition 0x000 to 0x001 compared to the ideal transition at 0 5 LSB Ideal value 0 LSB GND VCC PC5 ADC5 SCL PC4 ADC4 SDA PC3 ADC3 PC2 ADC2 PC1 ADC1 PC0 ADC0 ADC7 GND AREF AV...

Page 261: ...to the ideal transition at 1 5 LSB below maximum Ideal value 0 LSB Figure 24 11 Gain Error Integral Non linearity INL After adjusting for offset and gain error the INL is the maximum deviation of an actual transition compared to an ideal transition for any code Ideal value 0 LSB Output Code VREF Input Voltage Ideal ADC Actual ADC Offset Error Output Code VREF Input Voltage Ideal ADC Actual ADC Gai...

Page 262: ...tion Error Due to the quantization of the input voltage into a finite number of codes a range of input voltages 1 LSB wide will code to the same value Always 0 5 LSB Absolute accuracy The maximum deviation of an actual unadjusted transition compared to an ideal transition for any code This is the compound effect of offset gain error differential error non linearity and quantization error Ideal val...

Page 263: ...nverter can be used in single conversion mode to measure the voltage over the temperature sensor The measured voltage has a linear relationship to the temperature as described in Table 24 2 The voltage sensitivity is approximately 1 mV C and the accuracy of the temperature measure ment is 10 C The values described in Table 24 2 are typical values However due to the process variation the temperatur...

Page 264: ...he ADC Data Register immediately regardless of any ongoing conver sions For a complete description of this bit see ADCL and ADCH The ADC Data Register on page 267 Bit 4 Reserved This bit is an unused bit in the ATmega48A PA 88A PA 168A PA 328 P and will always read as zero Bits 3 0 MUX 3 0 Analog Channel Selection Bits The value of these bits selects which analog inputs are connected to the ADC Se...

Page 265: ...fter the ADC has been enabled or if ADSC is written at the same time as the ADC is enabled will take 25 ADC clock cycles instead of the normal 13 This first conversion performs initializa tion of the ADC ADSC will read as one as long as a conversion is in progress When the conversion is complete it returns to zero Writing zero to this bit has no effect Table 24 4 Input Channel Selections MUX3 0 Si...

Page 266: ...t ADIF is cleared by hardware when executing the corresponding interrupt handling vector Alter natively ADIF is cleared by writing a logical one to the flag Beware that if doing a Read Modify Write on ADCSRA a pending interrupt can be disabled This also applies if the SBI and CBI instructions are used Bit 3 ADIE ADC Interrupt Enable When this bit is written to one and the I bit in SREG is set the ...

Page 267: ...rved for future use To ensure compatibility with future devices these bits must be written to zero when ADCSRB is written Bit 2 0 ADTS 2 0 ADC Auto Trigger Source If ADATE in ADCSRA is written to one the value of these bits selects which source will trigger an ADC conversion If ADATE is cleared the ADTS 2 0 settings will have no effect A conver sion will be triggered by the rising edge of the sele...

Page 268: ...ll always read as zero when this bit is set When an analog signal is applied to the ADC5 0 pin and the digital input from this pin is not needed this bit should be written logic one to reduce power consumption in the digital input buffer Note that ADC pins ADC7 and ADC6 do not have digital input buffers and therefore do not require Digital Input Disable bits Table 24 6 ADC Auto Trigger Source Sele...

Page 269: ...hip debug system uses a One wire bi directional interface to control the program flow execute AVR instructions in the CPU and to program the different non volatile memories 25 3 Physical Interface When the debugWIRE Enable DWEN Fuse is programmed and Lock bits are unprogrammed the debugWIRE system within the target device is activated The RESET port pin is configured as a wire AND open drain bi di...

Page 270: ...rogrammed each time a Break Point is changed This is automatically handled by AVR Studio through the debugWIRE interface The use of Break Points will therefore reduce the Flash Data retention Devices used for debugging purposes should not be shipped to end customers 25 5 Limitations of debugWIRE The debugWIRE communication pin dW is physically located on the same pin as External Reset RESET An Ext...

Page 271: ... alternative 1 the Boot Loader provides an effective Read Modify Write feature which allows the user software to first read the page do the necessary changes and then write back the modified data If alter native 2 is used it is not possible to read the old data while loading since the page is already erased The temporary page buffer can be accessed in a random sequence It is essential that the pag...

Page 272: ...ddressing the Flash During Self Programming The Z pointer is used to address the SPM commands Since the Flash is organized in pages see Table 28 11 on page 302 the Program Counter can be treated as having two different sections One section consisting of the least significant bits is addressing the words within a page while the most significant bits are addressing the pages This is shown in Figure ...

Page 273: ...ed in the destination register The BLBSET and SELFPRGEN bits will auto clear upon completion of reading the Lock bits or if no LPM instruction is executed within three CPU cycles or no SPM instruction is executed within four CPU cycles When BLBSET and SELFPRGEN are cleared LPM will work as described in the Instruction set Manual The algorithm for reading the Fuse Low byte is similar to the one des...

Page 274: ... Similarly when reading the Extended Fuse byte EFB load 0x0002 in the Z pointer When an LPM instruction is executed within three cycles after the BLBSET and SELFPRGEN bits are set in the SPMCSR the value of the Extended Fuse byte will be loaded in the destination register as shown below See Table 28 5 on page 299 for detailed description and mapping of the Extended Fuse byte Fuse and Lock bits tha...

Page 275: ...ient power supply voltage This can be done by enabling the internal Brown out Detector BOD if the operating volt age matches the detection level If not an external low VCC reset protection circuit can be used If a reset occurs while a write operation is in progress the write operation will be completed provided that the power supply voltage is sufficient 2 Keep the AVR core in Power down sleep mod...

Page 276: ...e can be optimized at the expense of code size It is assumed that either the interrupt table is moved to the Boot loader section or that the interrupts are disabled equ PAGESIZEB PAGESIZE 2 PAGESIZEB is page size in BYTES not words org SMALLBOOTSTART Write_page Page Erase ldi spmcrval 1 PGERS 1 SELFPRGEN rcallDo_spm re enable the RWW section ldi spmcrval 1 RWWSRE 1 SELFPRGEN rcallDo_spm transfer d...

Page 277: ... section is not ready yet ret re enable the RWW section ldi spmcrval 1 RWWSRE 1 SELFPRGEN rcallDo_spm rjmp Return Do_spm check for previous SPM complete Wait_spm in temp1 SPMCSR sbrc temp1 SELFPRGEN rjmp Wait_spm input spmcrval determines SPM action disable interrupts if enabled store status in temp2 SREG cli check that no EEPROM write access is present Wait_ee sbic EECR EEPE rjmp Wait_ee SPM time...

Page 278: ... be lost Bit 3 BLBSET Boot Lock Bit Set The functionality of this bit in ATmega 48A 48PA is a subset of the functionality in ATmega88A 88PA 168A 168PA 328 328P An LPM instruction within three cycles after BLBSET and SELFPRGEN are set in the SPMCSR Register will read either the Lock bits or the Fuse bits depending on Z0 in the Z pointer into the destination register See Reading the Fuse and Lock Bi...

Page 279: ...struction will have a spe cial meaning see description above If only SELFPRGEN is written the following SPM instruction will store the value in R1 R0 in the temporary page buffer addressed by the Z pointer The LSB of the Z pointer is ignored The SELFPRGEN bit will auto clear upon completion of an SPM instruction or if no SPM instruction is executed within four clock cycles During Page Erase and Pa...

Page 280: ...he code if the feature is not needed anymore The size of the Boot Loader memory is configurable with fuses and the Boot Loader has two separate sets of Boot Lock bits which can be set independently This gives the user a unique flexibility to select different levels of protection 27 3 Application and Boot Loader Flash Sections The Flash memory is organized in two main sections the Application secti...

Page 281: ...te is programming a page inside the RWW section it is possible to read code from the Flash but only code that is located in the NRWW section During an on going programming the software must ensure that the RWW section never is being read If the user software is trying to read code that is located inside the RWW section i e by a call jmp lpm or an interrupt during programming the software might end...

Page 282: ...1 Read While Write vs No Read While Write Read While Write RWW Section No Read While Write NRWW Section Z pointer Addresses RWW Section Z pointer Addresses NRWW Section CPU is Halted During the Operation Code Located in NRWW Section Can be Read During the Operation ...

Page 283: ...d only The general Write Lock Lock Bit mode 2 does not control the programming of the Flash memory by SPM instruction Similarly the general Read Write Lock Lock Bit mode 1 does not control reading nor writing by LPM SPM if it is attempted 0x0000 Flashend Program Memory BOOTSZ 11 Application Flash Section Boot Loader Flash Section Flashend Program Memory BOOTSZ 10 0x0000 Program Memory BOOTSZ 01 Pr...

Page 284: ...ation section and LPM executing from the Boot Loader section is not allowed to read from the Application section If Interrupt Vectors are placed in the Boot Loader section interrupts are disabled while executing from the Application section 4 0 1 LPM executing from the Boot Loader section is not allowed to read from the Application section If Interrupt Vectors are placed in the Boot Loader section...

Page 285: ...other operations The only SPM operation that does not use the Z pointer is Setting the Boot Loader Lock bits The content of the Z pointer is ignored and will have no effect on the operation The LPM instruction does also use the Z pointer to store the address Since this instruction addresses the Flash byte by byte also the LSB bit Z0 of the Z pointer is used Figure 27 3 Addressing the Flash During ...

Page 286: ...SPMCSR and execute SPM within four clock cycles after writing SPMCSR The data in R1 and R0 is ignored The page address must be written to PCPAGE in the Z register Other bits in the Z pointer will be ignored during this operation Page Erase to the RWW section The NRWW section can be read during the Page Erase Page Erase to the NRWW section The CPU is halted during the operation 27 8 2 Filling the T...

Page 287: ...ssing the RWW section after the programming is completed the user software must clear the RWWSB by writing the RWWSRE See Simple Assembly Code Example for a Boot Loader on page 290 for an example 27 8 7 Setting the Boot Loader Lock Bits by SPM To set the Boot Loader Lock bits and general Lock Bits write the desired data to R0 write X0001001 to SPMCSR and execute SPM within four clock cycles after ...

Page 288: ... destination register as shown below Refer to Table 28 7 on page 299 for detailed description and mapping of the Fuse High byte When reading the Extended Fuse byte load 0x0002 in the Z pointer When an LPM instruction is executed within three cycles after the BLBSET and SELFPRGEN bits are set in the SPMCSR the value of the Extended Fuse byte EFB will be loaded in the destination register as shown b...

Page 289: ... power supply voltage This can be done by enabling the internal Brown out Detector BOD if the operating volt age matches the detection level If not an external low VCC reset protection circuit can be used If a reset occurs while a write operation is in progress the write operation will be completed provided that the power supply voltage is sufficient 3 Keep the AVR core in Power down sleep mode du...

Page 290: ...GESIZEB PAGESIZE 2 PAGESIZEB is page size in BYTES not words org SMALLBOOTSTART Write_page Page Erase ldi spmcrval 1 PGERS 1 SELFPRGEN call Do_spm re enable the RWW section ldi spmcrval 1 RWWSRE 1 SELFPRGEN call Do_spm transfer data from RAM to Flash page buffer ldi looplo low PAGESIZEB init loop variable ldi loophi high PAGESIZEB not required for PAGESIZEB 256 Wrloop ld r0 Y ld r1 Y ldi spmcrval ...

Page 291: ...rval 1 RWWSRE 1 SELFPRGEN call Do_spm rjmp Return Do_spm check for previous SPM complete Wait_spm in temp1 SPMCSR sbrc temp1 SELFPRGEN rjmp Wait_spm input spmcrval determines SPM action disable interrupts if enabled store status in temp2 SREG cli check that no EEPROM write access is present Wait_ee sbic EECR EEPE rjmp Wait_ee SPM timed sequence out SPMCSR spmcrval spm restore SREG to enable interr...

Page 292: ...words 8 0x000 0xEFF 0xF00 0xFFF 0xEFF 0xF00 0 1 512 words 16 0x000 0xDFF 0xE00 0xFFF 0xDFF 0xE00 0 0 1024 words 32 0x000 0xBFF 0xC00 0xFFF 0xBFF 0xC00 Table 27 8 Read While Write Limit ATmega88A 88PA Section Pages Address Read While Write section RWW 96 0x000 0xBFF No Read While Write section NRWW 32 0xC00 0xFFF Table 27 9 Explanation of Different Variables used in Figure 27 3 and the Mapping to t...

Page 293: ...0x0000 0x1EFF 0x1F00 0x1FFF 0x1EFF 0x1F00 0 1 512 words 8 0x0000 0x1DFF 0x1E00 0x1FFF 0x1DFF 0x1E00 0 0 1024 words 16 0x0000 0x1BFF 0x1C00 0x1FFF 0x1BFF 0x1C00 Table 27 11 Read While Write Limit ATmega168A 168PA Section Pages Address Read While Write section RWW 112 0x0000 0x1BFF No Read While Write section NRWW 16 0x1C00 0x1FFF Table 27 12 Explanation of Different Variables used in Figure 27 3 an...

Page 294: ...000 0x3DFF 0x3E00 0x3FFF 0x3DFF 0x3E00 0 1 1024 words 16 0x0000 0x3BFF 0x3C00 0x3FFF 0x3BFF 0x3C00 0 0 2048 words 32 0x0000 0x37FF 0x3800 0x3FFF 0x37FF 0x3800 Table 27 14 Read While Write Limit ATmega328 328P Section Pages Address Read While Write section RWW 224 0x0000 0x37FF No Read While Write section NRWW 32 0x3800 0x3FFF Table 27 15 Explanation of Different Variables used in Figure 27 3 and t...

Page 295: ...ust wait until the programming is completed SELFPRGEN will be cleared Then if the RWWSRE bit is written to one at the same time as SELFPRGEN the next SPM instruction within four clock cycles re enables the RWW section The RWW section cannot be re enabled while the Flash is busy with a Page Erase or a Page Write SELFPRGEN is set If the RWWSRE bit is written while the Flash is being loaded the Flash...

Page 296: ...uted within four clock cycles The CPU is halted dur ing the entire Page Write operation if the NRWW section is addressed Bit 0 SELFPRGEN Self Programming Enable This bit enables the SPM instruction for the next four clock cycles If written to one together with either RWWSRE BLBSET PGWRT or PGERS the following SPM instruction will have a spe cial meaning see description above If only SELFPRGEN is w...

Page 297: ...t Lock bits before programming the LB1 and LB2 2 1 means unprogrammed 0 means programmed Table 28 1 Lock Bit Byte 1 Lock Bit Byte Bit No Description Default Value 7 1 unprogrammed 6 1 unprogrammed BLB12 2 5 Boot Lock bit 1 unprogrammed BLB11 2 4 Boot Lock bit 1 unprogrammed BLB02 2 3 Boot Lock bit 1 unprogrammed BLB01 2 2 Boot Lock bit 1 unprogrammed LB2 1 Lock bit 1 unprogrammed LB1 0 Lock bit 1 ...

Page 298: ...ile executing from the Application section 4 0 1 LPM executing from the Boot Loader section is not allowed to read from the Application section If Interrupt Vectors are placed in the Boot Loader section interrupts are disabled while executing from the Application section BLB1 Mode BLB12 BLB11 1 1 1 No restrictions for SPM or LPM accessing the Boot Loader section 2 1 0 SPM is not allowed to write t...

Page 299: ... page 293 for details 0 programmed 1 BOOTRST 0 Select Reset Vector 1 unprogrammed Table 28 6 Extended Fuse Byte for ATmega328 328P Extended Fuse Byte Bit No Description Default Value 7 1 6 1 5 1 4 1 3 1 BODLEVEL2 1 2 Brown out Detector trigger level 1 unprogrammed BODLEVEL1 1 1 Brown out Detector trigger level 1 unprogrammed BODLEVEL0 1 0 Brown out Detector trigger level 1 unprogrammed Table 28 7 ...

Page 300: ...programmed BODLEVEL1 4 1 Brown out Detector trigger level 1 unprogrammed BODLEVEL0 4 0 Brown out Detector trigger level 1 unprogrammed Table 28 8 Fuse High Byte for ATmega328 328P High Fuse Byte Bit No Description Default Value RSTDISBL 1 7 External Reset Disable 1 unprogrammed DWEN 6 debugWIRE Enable 1 unprogrammed SPIEN 2 5 Enable Serial Program and Data Downloading 0 programmed SPI programming ...

Page 301: ...SAVE Fuse which will take effect once it is programmed The fuses are also latched on Power up in Normal mode 28 3 Signature Bytes All Atmel microcontrollers have a three byte signature code which identifies the device This code can be read in both serial and parallel mode also when the device is locked The three bytes reside in a separate address space For the ATmega48A PA 88A PA 168A PA 328 P the...

Page 302: ... Page Size PCWORD No of Pages PCPAGE PCMSB ATmega48A 2K words 4Kbytes 32 words PC 4 0 64 PC 10 5 10 ATmega48PA 2K words 4Kbytes 32 words PC 4 0 64 PC 10 5 10 ATmega88A 4K words 8Kbytes 32 words PC 4 0 128 PC 11 5 11 ATmega88PA 4K words 8Kbytes 32 words PC 4 0 128 PC 11 5 11 ATmega168A 8K words 16Kbytes 64 words PC 5 0 128 PC 12 6 12 ATmega168PA 8K words 16Kbytes 64 words PC 5 0 128 PC 12 6 12 ATme...

Page 303: ...pin names The XA1 XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse The bit coding is shown in Table 28 15 When pulsing WR or OE the command loaded determines the action executed The different Commands are shown in Table 28 16 Figure 28 1 Parallel Programming Note VCC 0 3V AVCC VCC 0 3V however AVCC should always be within 4 5 5 5V ATmega168A 512bytes 4bytes EEA 1...

Page 304: ...ts Low byte 1 selects 2 nd High byte DATA PC 1 0 PB 5 0 I O Bi directional Data bus Output when OE is low Table 28 14 Pin Values Used to Enter Programming Mode Pin Symbol Value PAGEL Prog_enable 3 0 XA1 Prog_enable 2 0 XA0 Prog_enable 1 0 BS1 Prog_enable 0 0 Table 28 15 XA1 and XA0 Coding XA1 XA0 Action when XTAL1 is Pulsed 0 0 Load Flash or EEPROM Address High or low address byte determined by BS...

Page 305: ...GND 3 Monitor VCC and as soon as VCC reaches 0 9 1 1V apply 11 5 12 5V to RESET 4 Keep the Prog_enable pins unchanged for at least 10µs after the High voltage has been applied to ensure the Prog_enable Signature has been latched 5 Wait until VCC actually reaches 4 5 5 5V before giving any parallel programming commands 6 Exit Programming mode by power the device down or by bringing RESET pin to 0V ...

Page 306: ...program data to be pro grammed simultaneously The following procedure describes how to program the entire Flash memory A Load Command Write Flash 1 Set XA1 XA0 to 10 This enables command loading 2 Set BS1 to 0 3 Set DATA to 0001 0000 This is the command for Write Flash 4 Give XTAL1 a positive pulse This loads the command B Load Address Low byte 1 Set XA1 XA0 to 00 This enables address loading 2 Se...

Page 307: ...address high byte H Program Page 1 Give WR a negative pulse This starts programming of the entire page of data RDY BSY goes low 2 Wait until RDY BSY goes high See Figure 28 3 for signal waveforms I Repeat B through H until the entire Flash is programmed or until all data has been programmed J End Page Programming 1 1 Set XA1 XA0 to 10 This enables command loading 2 Set DATA to 0000 0000 This is th...

Page 308: ...ramming the Flash on page 306 for details on Command Address and Data loading 1 A Load Command 0001 0001 2 G Load Address High Byte 0x00 0xFF 3 B Load Address Low Byte 0x00 0xFF 4 C Load Data 0x00 0xFF 5 E Latch data give PAGEL a positive pulse K Repeat 3 through 5 until the entire buffer is filled L Program EEPROM page 1 Set BS1 to 0 2 Give WR a negative pulse This starts programming of the EEPRO...

Page 309: ...Command and Address loading 1 A Load Command 0000 0011 2 G Load Address High Byte 0x00 0xFF 3 B Load Address Low Byte 0x00 0xFF 4 Set OE to 0 and BS1 to 0 The EEPROM Data byte can now be read at DATA 5 Set OE to 1 28 7 8 Programming the Fuse Low Bits The algorithm for programming the Fuse Low bits is as follows refer to Programming the Flash on page 306 for details on Command and Data loading 1 A ...

Page 310: ... extended data byte 4 4 Give WR a negative pulse and wait for RDY BSY to go high 5 5 Set BS2 to 0 This selects low data byte Figure 28 5 Programming the FUSES Waveforms 28 7 11 Programming the Lock Bits The algorithm for programming the Lock bits is as follows refer to Programming the Flash on page 306 for details on Command and Data loading 1 A Load Command 0010 0000 2 C Load Data Low Byte Bit n ...

Page 311: ...read at DATA 0 means programmed 6 Set OE to 1 Figure 28 6 Mapping Between BS1 BS2 and the Fuse and Lock Bits During Read 28 7 13 Reading the Signature Bytes The algorithm for reading the Signature bytes is as follows refer to Programming the Flash on page 306 for details on Command and Address loading 1 A Load Command 0000 1000 2 B Load Address Low Byte 0x00 0x02 3 Set OE to 0 and BS1 to 0 The sel...

Page 312: ...erface Figure 28 7 Serial Programming and Verify 1 Notes 1 If the device is clocked by the internal Oscillator it is no need to connect a clock source to the XTAL1 pin 2 VCC 0 3V AVCC VCC 0 3V however AVCC should always be within 1 8 5 5V When programming the EEPROM an auto erase cycle is built into the self timed programming operation in the Serial mode ONLY and there is no need to first execute ...

Page 313: ...s loaded one byte at a time by supplying the 6 LSB of the address and data together with the Load Program Memory Page instruction To ensure correct loading of the page the data low byte must be loaded before data high byte is applied for a given address The Program Memory Page is stored by loading the Write Program Memory Page instruction with the 7 MSB of the address If polling RDY BSY is not use...

Page 314: ..._EEPROM 3 6ms tWD_ERASE 9 0ms Table 28 19 Serial Programming Instruction Set Hexadecimal values Instruction Operation Instruction Format Byte 1 Byte 2 Byte 3 Byte4 Programming Enable AC 53 00 00 Chip Erase Program Memory EEPROM AC 80 00 00 Poll RDY BSY F0 00 00 data byte out Load Instructions Load Extended Address byte 1 4D 00 Extended adr 00 Load Program Memory Page High byte 48 00 adr LSB high d...

Page 315: ...eration is still pending Wait until this bit returns 0 before the next instruction is carried out Within the same page the low data byte must be loaded prior to the high data byte After data is loaded to the page buffer program the EEPROM page see Figure 28 8 on page 316 Read Calibration Byte 38 00 00 data byte out Write Instructions 6 Write Program Memory Page 4C adr MSB 8 adr LSB 8 00 Write EEPR...

Page 316: ...25 Byte 1 Byte 2 Byte 3 Byte 4 Adr LSB Bit 15 B 0 Serial Programming Instruction Program Memory EEPROM Memory Page 0 Page 1 Page 2 Page N 1 Page Buffer Write Program Memory Page Write EEPROM Memory Page Load Program Memory Page High Low Byte Load EEPROM Memory Page page access Byte 1 Byte 2 Byte 3 Byte 4 Bit 15 B 0 Adr MSB Page Offset Page Number Adr M MS SB A A Adr r L LSB B MSB MSB LSB LSB SERIA...

Page 317: ... unless otherwise noted Symbol Parameter Condition Min Typ Max Units VIL Input Low Voltage except XTAL1 and RESET pin VCC 1 8V 2 4V VCC 2 4V 5 5V 0 5 0 5 0 2VCC 1 0 3VCC 1 V VIH Input High Voltage except XTAL1 and RESET pins VCC 1 8V 2 4V VCC 2 4V 5 5V 0 7VCC 2 0 6VCC 2 VCC 0 5 VCC 0 5 V VIL1 Input Low Voltage XTAL1 pin VCC 1 8V 5 5V 0 5 0 1VCC 1 V VIH1 Input High Voltage XTAL1 pin VCC 1 8V 2 4V V...

Page 318: ... exceed 100 mA 3 The sum of all IOL for ports D0 D4 RESET should not exceed 100 mA If IOL exceeds the test condition VOL may exceed the related specification Pins are not guaranteed to sink current greater than the listed test condition 29 2 1 ATmega48A DC Characteristics Notes 1 Values with Minimizing Power Consumption enabled 0xFF RRST Reset Pull up Resistor 30 60 kΩ RPU I O Pin Pull up Resistor...

Page 319: ...Max Units ICC Power Supply Current 1 Active 1MHz VCC 2V 0 2 0 5 mA Active 4MHz VCC 3V 1 2 2 5 mA Active 8MHz VCC 5V 4 0 9 mA Idle 1MHz VCC 2V 0 03 0 15 mA Idle 4MHz VCC 3V 0 21 0 7 mA Idle 8MHz VCC 5V 0 9 2 7 mA Power save mode 3 32kHz TOSC enabled VCC 1 8V 0 75 µA 32kHz TOSC enabled VCC 3V 0 9 µA Power down mode 3 WDT enabled VCC 3V 3 9 8 µA WDT disabled VCC 3V 0 1 2 µA Table 29 4 ATmega88A DC ch...

Page 320: ... Power Supply Current 1 Active 1MHz VCC 2V 0 2 0 5 mA Active 4MHz VCC 3V 1 2 2 5 mA Active 8MHz VCC 5V 4 1 9 mA Idle 1MHz VCC 2V 0 03 0 15 mA Idle 4MHz VCC 3V 0 18 0 7 mA Idle 8MHz VCC 5V 0 8 2 7 mA Power save mode 3 32kHz TOSC enabled VCC 1 8V 0 8 µA 32kHz TOSC enabled VCC 3V 0 9 µA Power down mode 3 WDT enabled VCC 3V 3 9 8 µA WDT disabled VCC 3V 0 1 2 µA Table 29 6 ATmega168A Dc characteristics...

Page 321: ...C Power Supply Current 1 Active 1MHz VCC 2V 0 2 0 5 mA Active 4MHz VCC 3V 1 2 2 5 mA Active 8MHz VCC 5V 4 2 9 mA Idle 1MHz VCC 2V 0 03 0 15 mA Idle 4MHz VCC 3V 0 2 0 7 mA Idle 8MHz VCC 5V 0 9 2 7 Power save mode 3 32kHz TOSC enabled VCC 1 8V 0 75 µA 32kHz TOSC enabled VCC 3V 0 83 µA Power down mode 3 WDT enabled VCC 3V 4 1 8 µA WDT disabled VCC 3V 0 1 2 µA Table 29 8 ATmega328 Dc characteristics T...

Page 322: ...rve is linear between 1 8V VCC 2 7V and between 2 7V VCC 4 5V Figure 29 1 Maximum Frequency vs VCC Table 29 9 ATmega328P Dc characteristics TA 40 C to 85 C VCC 1 8V to 5 5V unless otherwise noted Symbol Parameter Condition Min Typ 2 Max Units ICC Power Supply Current 1 Active 1MHz VCC 2V 0 3 0 5 mA Active 4MHz VCC 3V 1 7 2 5 mA Active 8MHz VCC 5V 5 2 9 mA Idle 1MHz VCC 2V 0 04 0 15 mA Idle 4MHz VC...

Page 323: ...ng design targets and will be updated after characterization of actual silicon Table 29 10 Calibration Accuracy of Internal RC Oscillator Frequency VCC Temperature Calibration Accuracy Factory Calibration 8 0MHz 3V 25 C 10 User Calibration 7 3 8 1MHz 1 8V 5 5V 40 C 85 C 1 VIL1 VIH1 Table 29 11 External Clock Drive Symbol Parameter VCC 1 8 5 5V VCC 2 7 5 5V VCC 4 5 5 5V Units Min Max Min Max Min Ma...

Page 324: ... 85 C in production Table 29 12 Reset Brown out and Internal Voltage Characteristics 1 Symbol Parameter Min Typ Max Units VPOT Power on Reset Threshold Voltage rising 1 1 1 4 1 6 V Power on Reset Threshold Voltage falling 2 0 6 1 3 1 6 V SRON Power on Slope Rate 0 01 10 V ms VRST RESET Pin Threshold Voltage 0 2 VCC 0 9 VCC V tRST Minimum pulse width on RESET Pin 2 5 µs VHYST Brown out Detector Hys...

Page 325: ...inary values representing design targets and will be updated after character ization of actual silicon Table 29 14 SPI Timing Parameters Description Mode Min Typ Max 1 SCK period Master See Table 19 5 ns 2 SCK high low Master 50 duty cycle 3 Rise Fall time Master 3 6 4 Setup Master 10 5 Hold Master 10 6 Out to SCK Master 0 5 tsck 7 SCK to out Master 10 8 SCK to out high Master 10 9 SS low to out S...

Page 326: ...ming Requirements Master Mode Figure 29 4 SPI Interface Timing Requirements Slave Mode MOSI Data Output SCK CPOL 1 MISO Data Input SCK CPOL 0 SS MSB LSB LSB MSB 6 1 2 2 3 4 5 8 7 MISO Data Output SCK CPOL 1 MOSI Data Input SCK CPOL 0 SS MSB LSB LSB MSB 10 11 11 12 13 14 17 15 9 X 16 ...

Page 327: ...0 0 1Cb 3 2 250 ns tSP 1 Spikes Suppressed by Input Filter 0 50 2 ns Ii Input Current each I O Pin 0 1VCC Vi 0 9VCC 10 10 µA Ci 1 Capacitance for each I O Pin 10 pF fSCL SCL Clock Frequency fCK 4 max 16fSCL 250kHz 5 0 400 kHz Rp Value of Pull up resistor fSCL 100kHz fSCL 100kHz tHD STA Hold Time repeated START Condition fSCL 100kHz 4 0 µs fSCL 100kHz 0 6 µs tLOW Low Period of the SCL Clock fSCL 10...

Page 328: ...kHz 3 Cb capacitance of one bus line in pF 4 fCK CPU clock frequency 5 This requirement applies to all ATmega48A PA 88A PA 168A PA 328 P 2 wire Serial Interface operation Other devices con nected to the 2 wire Serial Bus need only obey the general fSCL requirement Figure 29 5 Two wire Serial Bus Timing tSU STA tLOW tHIGH tLOW tof tHD STA tHD DAT tSU DAT tSU STO tBUF SCL SDA tr ...

Page 329: ...REF 4V VCC 4V ADC clock 1MHz Noise Reduction Mode 4 5 LSB Integral Non Linearity INL VREF 4V VCC 4V ADC clock 200kHz 0 5 LSB Differential Non Linearity DNL VREF 4V VCC 4V ADC clock 200kHz 0 25 LSB Gain Error VREF 4V VCC 4V ADC clock 200kHz 2 LSB Offset Error VREF 4V VCC 4V ADC clock 200kHz 2 LSB Conversion Time Free Running Conversion 13 260 µs Clock Frequency 50 1000 kHz AVCC 1 Analog Supply Volt...

Page 330: ...XHXL XTAL1 Pulse Width High 150 ns tXLDX Data and Control Hold after XTAL1 Low 67 ns tXLWL XTAL1 Low to WR Low 0 ns tXLPH XTAL1 Low to PAGEL high 0 ns tPLXH PAGEL low to XTAL1 high 150 ns tBVPH BS1 Valid before PAGEL High 67 ns tPHPL PAGEL Pulse Width High 150 ns tPLBX BS1 Hold after PAGEL Low 67 ns tWLBX BS2 1 Hold after WR Low 67 ns tPLWL PAGEL Low to WR Low 67 ns tBVWL BS1 Valid to WR Low 67 ns...

Page 331: ... 1 Note 1 The timing requirements shown in Figure 29 6 i e tDVXH tXHXL and tXLDX also apply to read ing operation Data Contol DATA XA0 1 BS1 BS2 XTAL1 tXHXL tWLWH tDVXH tXLDX tPLWL tWLRH WR RDY BSY PAGEL tPHPL tPLBX tBVPH tXLWL tWLBX tBVWL WLRL XTAL1 PAGEL tPLXH XLXH t tXLPH ADDR0 Low Byte DATA Low Byte DATA High Byte ADDR1 Low Byte DATA BS1 XA0 XA1 LOAD ADDRESS LOW BYTE LOAD DATA LOW BYTE LOAD DA...

Page 332: ...olled by the Power Reduction Register See Power Reduction Regis ter on page 43 for details The power consumption in Power down mode is independent of clock selection The current consumption is a function of several factors such as operating voltage operating frequency loading of I O pins switching rate of I O pins code executed and ambient tempera ture The dominating factors are operating voltage ...

Page 333: ...Active Supply Current vs Low Frequency 0 1 1 0MHz Figure 30 2 ATmega48A Active Supply Current vs Frequency 1 20MHz 5 5 V 5 0 V 4 5 V 4 0 V 3 3 V 2 7 V 1 8 V 0 0 2 0 4 0 6 0 8 1 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz I CC mA 5 5 V 5 0 V 4 5 V 0 2 4 6 8 10 12 0 2 4 6 8 10 12 14 16 18 20 Frequency MHz I CC mA 1 8 V 2 7 V 3 3 V 4 0 V ...

Page 334: ...rent vs VCC Internal RC Oscillator 128kHz Figure 30 4 ATmega48A Active Supply Current vs VCC Internal RC Oscillator 1MHz 85 C 25 C 40 C 0 0 02 0 04 0 06 0 08 0 1 0 12 0 14 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA 85 C 25 C 40 C 0 0 2 0 4 0 6 0 8 1 1 2 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 335: ...llator 8MHz 30 1 2 Idle Supply Current Figure 30 6 ATmega48A Idle Supply Current vs Low Frequency 0 1 1 0MHz 85 C 25 C 40 C 0 1 2 3 4 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA 5 5 V 5 0 V 4 5 V 4 0 V 3 3 V 2 7 V 1 8 V 0 0 02 0 04 0 06 0 08 0 1 0 12 0 14 0 16 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz I CC mA ...

Page 336: ...requency 1 20MHz Figure 30 8 ATmega48A Idle Supply Current vs VCC Internal RC Oscillator 128kHz 5 5 V 5 0 V 4 5 V 0 0 5 1 1 5 2 2 5 3 0 2 4 6 8 10 12 14 16 18 20 Frequency MHz I CC mA 1 8 V 2 7 V 3 3 V 4 0 V 85 C 25 C 40 C 0 0 007 0 014 0 021 0 028 0 035 0 042 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 337: ...urrent vs VCC Internal RC Oscillator 1MHz Figure 30 10 ATmega48A Idle Supply Current vs Vcc Internal RC Oscillator 8MHz 85 C 25 C 40 C 0 0 05 0 1 0 15 0 2 0 25 0 3 0 35 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA 85 C 25 C 40 C 0 0 2 0 4 0 6 0 8 1 1 2 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 338: ... Figure 30 53 on page 360 we find that the idle current consumption is 0 028 mA at VCC 2 0V and F 1MHz The total current consumption in idle mode with TIMER1 ADC and SPI enabled gives Table 30 1 ATmega48PA Additional Current Consumption for the different I O modules absolute values PRR bit Typical numbers VCC 2V F 1MHz VCC 3V F 4MHz VCC 5V F 8MHz PRUSART0 2 9uA 20 7uA 97 4uA PRTWI 6 0uA 44 8uA 219...

Page 339: ... 11 ATmega48A Power Down Supply Current vs VCC Watchdog Timer Disabled Figure 30 12 ATmega48A Power Down Supply Current vs VCC Watchdog Timer Enabled 85 C 25 C 40 C 0 0 2 0 4 0 6 0 8 1 1 2 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA 85 C 25 C 40 C 0 2 4 6 8 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ...

Page 340: ...nd 32kHz Crystal Oscillator Running 30 1 6 Standby Supply Current Figure 30 14 ATmega48A Standby Supply Current vs Vcc Watchdog Timer Disabled 85 C 25 C 40 C 0 0 4 0 8 1 2 1 6 2 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA 6MHz_xtal 6MHz_res 4MHz_xtal 4MHz_res 450kHz_res 2MHz_xtal 2MHz_res 0 0 02 0 04 0 06 0 08 0 1 0 12 0 14 0 16 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 341: ... I O Pin Pull up Resistor Current vs Input Voltage VCC 1 8 V Figure 30 16 ATmega48A I O Pin Pull up Resistor Current vs Input Voltage VCC 2 7 V 85 C 25 C 40 C 0 10 20 30 40 50 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 VOP V I OP uA 85 C 25 C 40 C 0 10 20 30 40 50 60 70 0 0 5 1 1 5 2 2 5 3 VOP V I OP uA ...

Page 342: ...l up Resistor Current vs Input Voltage VCC 5V Figure 30 18 ATmega48A Reset Pull up Resistor Current vs Reset Pin Voltage VCC 1 8V 85 C 25 C 40 C 0 20 40 60 80 100 120 140 0 1 2 3 4 5 VOP V I OP uA 85 C 25 C 40 C 0 5 10 15 20 25 30 35 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 VRESET V I RESET uA ...

Page 343: ...Resistor Current vs Reset Pin Voltage VCC 2 7 V Figure 30 20 ATmega48A Reset Pull up Resistor Current vs Reset Pin Voltage VCC 5V 85 C 25 C 40 C 0 10 20 30 40 50 60 0 0 5 1 1 5 2 2 5 3 VRESET V I RESET uA 85 C 25 C 40 C 0 20 40 60 80 100 120 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 VRESET V I RESET uA ...

Page 344: ...ngth Figure 30 21 ATmega48A I O Pin Output Voltage vs Sink Current VCC 3 V Figure 30 22 ATmega48A I O Pin Output Voltage vs Sink Current VCC 5 V 85 C 25 C 40 C 0 0 2 0 4 0 6 0 8 1 0 4 8 12 16 20 IOL mA V OL V 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 0 4 8 12 16 20 IOL mA V OL V ...

Page 345: ...ga48A I O Pin Output Voltage vs Source Current Vcc 3 V Figure 30 24 ATmega48A I O Pin Output Voltage vs Source Current VCC 5 V 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 3 3 5 0 4 8 12 16 20 IOH mA V OH V 85 C 25 C 40 C 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 4 8 12 16 20 IOH mA V OH V ...

Page 346: ...a48A I O Pin Input Threshold Voltage vs VCC VIH I O Pin read as 1 Figure 30 26 ATmega48A I O Pin Input Threshold Voltage vs VCC VIL I O Pin read as 0 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 3 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V ...

Page 347: ...Pin Input Hysteresis vs VCC Figure 30 28 ATmega48A Reset Input Threshold Voltage vs VCC VIH I O Pin read as 1 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Input Hysteresis V 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V ...

Page 348: ...nput Threshold Voltage vs VCC VIL I O Pin read as 0 Figure 30 30 ATmega48A Reset Pin Input Hysteresis vs VCC 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Input Hysteresis V ...

Page 349: ... is 1 8 V Figure 30 32 ATmega48A BOD Thresholds vs Temperature BODLEVEL is 2 7 V Rising Vcc Falling Vcc 1 79 1 8 1 81 1 82 1 83 1 84 1 85 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 Temperature C Threshold V Rising Vcc Falling Vcc 2 62 2 64 2 66 2 68 2 7 2 72 2 74 2 76 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 Temperature C Threshold V ...

Page 350: ...re BODLEVEL is 4 3 V Figure 30 34 ATmega48A Bandgap Voltage vs VCC Rising Vcc Falling Vcc 4 24 4 26 4 28 4 3 4 32 4 34 4 36 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 Temperature C Threshold V 85 C 25 C 40 C 1 09 1 092 1 094 1 096 1 098 1 1 1 102 1 104 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Bandgap Voltage V ...

Page 351: ...8A Watchdog Oscillator Frequency vs Temperature Figure 30 36 ATmega48A Watchdog Oscillator Frequency vs VCC 5 5 V 4 0 V 3 3 V 2 7 V 104 106 108 110 112 114 116 40 30 20 10 0 10 20 30 40 50 60 70 80 90 Temperature C F RC kHz 85 C 25 C 40 C 106 108 110 112 114 116 118 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V F RC kHz ...

Page 352: ...scillator Frequency vs VCC Figure 30 38 ATmega48A Calibrated 8MHz RC Oscillator Frequency vs Temperature 85 C 25 C 40 C 7 6 7 7 7 8 7 9 8 8 1 8 2 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V F RC MHz 5 5 V 3 3 V 1 8 V 7 6 7 7 7 8 7 9 8 8 1 8 2 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 Temperature C F RC MHz ...

Page 353: ... vs OSCCAL Value 30 1 12 Current Consumption of Peripheral Units Figure 30 40 ATmega48A ADC Current vs VCC AREF AVCC 85 C 25 C 40 C 0 2 4 6 8 10 12 14 16 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL X1 F RC MHz 85 C 25 C 40 C 0 50 100 150 200 250 300 350 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ...

Page 354: ...ga48A Analog Comparator Current vs VCC Figure 30 42 ATmega48A AREF External Reference Current vs VCC 85 C 25 C 40 C 0 10 20 30 40 50 60 70 80 90 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA 85 C 25 C 40 C 0 20 40 60 80 100 120 140 160 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ...

Page 355: ... P Figure 30 43 ATmega48A Brownout Detector Current vs VCC Figure 30 44 ATmega48A Programming Current vs VCC 85 C 25 C 40 C 0 8 16 24 32 40 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA 85 C 25 C 40 C 0 1 2 3 4 5 6 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 356: ...Current vs Low Frequency 0 1 1 0MHz Figure 30 46 ATmega48A Reset Supply Current vs Frequency 1 20MHz 5 5 V 5 0 V 4 5 V 4 0 V 3 3 V 2 7 V 1 8 V 0 0 02 0 04 0 06 0 08 0 1 0 12 0 14 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz I CC mA 5 5 V 5 0 V 4 5 V 0 0 5 1 1 5 2 2 5 0 2 4 6 8 10 12 14 16 18 20 Frequency MHz I CC mA 1 8 V 2 7 V 3 3 V 4 0 V ...

Page 357: ...8271D AVR 05 11 ATmega48A PA 88A PA 168A PA 328 P Figure 30 47 ATmega48A Minimum Reset Pulse width vs VCC 85 C 25 C 40 C 0 200 400 600 800 1000 1200 1400 1600 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Pulsewidth ns ...

Page 358: ...Active Supply Current vs Low Frequency 0 1 1 0MHz Figure 30 49 ATmega48PA Active Supply Current vs Frequency 1 20MHz 5 5 V 5 0 V 4 5 V 4 0 V 3 3 V 2 7 V 1 8 V 0 0 2 0 4 0 6 0 8 1 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz I CC mA 5 5 V 5 0 V 4 5 V 0 2 4 6 8 10 12 0 2 4 6 8 10 12 14 16 18 20 Frequency MHz I CC mA 1 8 V 2 7 V 3 3 V 4 0 V ...

Page 359: ...rent vs VCC Internal RC Oscillator 128kHz Figure 30 51 ATmega48PA Active Supply Current vs VCC Internal RC Oscillator 1MHz 85 C 25 C 40 C 0 0 02 0 04 0 06 0 08 0 1 0 12 0 14 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA 85 C 25 C 40 C 0 0 2 0 4 0 6 0 8 1 1 2 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 360: ...llator 8MHz 30 2 2 Idle Supply Current Figure 30 53 ATmega48PA Idle Supply Current vs Low Frequency 0 1 1 0MHz 85 C 25 C 40 C 0 1 2 3 4 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA 5 5 V 5 0 V 4 5 V 4 0 V 3 3 V 2 7 V 1 8 V 0 0 02 0 04 0 06 0 08 0 1 0 12 0 14 0 16 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz I CC mA ...

Page 361: ...requency 1 20MHz Figure 30 55 ATmega48PA Idle Supply Current vs VCC Internal RC Oscillator 128kHz 5 5 V 5 0 V 4 5 V 0 0 5 1 1 5 2 2 5 3 0 2 4 6 8 10 12 14 16 18 20 Frequency MHz I CC mA 1 8 V 2 7 V 3 3 V 4 0 V 85 C 25 C 40 C 0 0 007 0 014 0 021 0 028 0 035 0 042 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 362: ...urrent vs VCC Internal RC Oscillator 1MHz Figure 30 57 ATmega48PA Idle Supply Current vs Vcc Internal RC Oscillator 8MHz 85 C 25 C 40 C 0 0 05 0 1 0 15 0 2 0 25 0 3 0 35 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA 85 C 25 C 40 C 0 0 2 0 4 0 6 0 8 1 1 2 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 363: ... Figure 30 53 on page 360 we find that the idle current consumption is 0 028 mA at VCC 2 0V and F 1MHz The total current consumption in idle mode with TIMER1 ADC and SPI enabled gives Table 30 3 ATmega48PA Additional Current Consumption for the different I O modules absolute values PRR bit Typical numbers VCC 2V F 1MHz VCC 3V F 4MHz VCC 5V F 8MHz PRUSART0 2 9uA 20 7uA 97 4uA PRTWI 6 0uA 44 8uA 219...

Page 364: ...58 ATmega48PA Power Down Supply Current vs VCC Watchdog Timer Disabled Figure 30 59 ATmega48PA Power Down Supply Current vs VCC Watchdog Timer Enabled 85 C 25 C 40 C 0 0 2 0 4 0 6 0 8 1 1 2 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA 85 C 25 C 40 C 0 2 4 6 8 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ...

Page 365: ...nd 32kHz Crystal Oscillator Running 30 2 6 Standby Supply Current Figure 30 61 ATmega48PA Standby Supply Current vs Vcc Watchdog Timer Disabled 85 C 25 C 40 C 0 0 4 0 8 1 2 1 6 2 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA 6MHz_xtal 6MHz_res 4MHz_xtal 4MHz_res 450kHz_res 2MHz_xtal 2MHz_res 0 0 02 0 04 0 06 0 08 0 1 0 12 0 14 0 16 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 366: ... I O Pin Pull up Resistor Current vs Input Voltage VCC 1 8 V Figure 30 63 ATmega48PA I O Pin Pull up Resistor Current vs Input Voltage VCC 2 7 V 85 C 25 C 40 C 0 10 20 30 40 50 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 VOP V I OP uA 85 C 25 C 40 C 0 10 20 30 40 50 60 70 0 0 5 1 1 5 2 2 5 3 VOP V I OP uA ...

Page 367: ... up Resistor Current vs Input Voltage VCC 5 V Figure 30 65 ATmega48PA Reset Pull up Resistor Current vs Reset Pin Voltage VCC 1 8 V 85 C 25 C 40 C 0 20 40 60 80 100 120 140 0 1 2 3 4 5 VOP V I OP uA 85 C 25 C 40 C 0 5 10 15 20 25 30 35 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 VRESET V I RESET uA ...

Page 368: ...esistor Current vs Reset Pin Voltage VCC 2 7 V Figure 30 67 ATmega48PA Reset Pull up Resistor Current vs Reset Pin Voltage VCC 5 V 85 C 25 C 40 C 0 10 20 30 40 50 60 0 0 5 1 1 5 2 2 5 3 VRESET V I RESET uA 85 C 25 C 40 C 0 20 40 60 80 100 120 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 VRESET V I RESET uA ...

Page 369: ...gth Figure 30 68 ATmega48PA I O Pin Output Voltage vs Sink Current VCC 3 V Figure 30 69 ATmega48PA I O Pin Output Voltage vs Sink Current VCC 5 V 85 C 25 C 40 C 0 0 2 0 4 0 6 0 8 1 0 4 8 12 16 20 IOL mA V OL V 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 0 4 8 12 16 20 IOL mA V OL V ...

Page 370: ...a48PA I O Pin Output Voltage vs Source Current Vcc 3 V Figure 30 71 ATmega48PA I O Pin Output Voltage vs Source Current VCC 5 V 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 3 3 5 0 4 8 12 16 20 IOH mA V OH V 85 C 25 C 40 C 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 4 8 12 16 20 IOH mA V OH V ...

Page 371: ...48PA I O Pin Input Threshold Voltage vs VCC VIH I O Pin read as 1 Figure 30 73 ATmega48PA I O Pin Input Threshold Voltage vs VCC VIL I O Pin read as 0 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 3 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V ...

Page 372: ...Pin Input Hysteresis vs VCC Figure 30 75 ATmega48PA Reset Input Threshold Voltage vs VCC VIH I O Pin read as 1 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Input Hysteresis V 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V ...

Page 373: ...nput Threshold Voltage vs VCC VIL I O Pin read as 0 Figure 30 77 ATmega48PA Reset Pin Input Hysteresis vs VCC 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Input Hysteresis V ...

Page 374: ... is 1 8 V Figure 30 79 ATmega48PA BOD Thresholds vs Temperature BODLEVEL is 2 7 V Rising Vcc Falling Vcc 1 79 1 8 1 81 1 82 1 83 1 84 1 85 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 Temperature C Threshold V Rising Vcc Falling Vcc 2 62 2 64 2 66 2 68 2 7 2 72 2 74 2 76 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 Temperature C Threshold V ...

Page 375: ...re BODLEVEL is 4 3 V Figure 30 81 ATmega48PA Bandgap Voltage vs VCC Rising Vcc Falling Vcc 4 24 4 26 4 28 4 3 4 32 4 34 4 36 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 Temperature C Threshold V 85 C 25 C 40 C 1 09 1 092 1 094 1 096 1 098 1 1 1 102 1 104 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Bandgap Voltage V ...

Page 376: ...PA Watchdog Oscillator Frequency vs Temperature Figure 30 83 ATmega48PA Watchdog Oscillator Frequency vs VCC 5 5 V 4 0 V 3 3 V 2 7 V 104 106 108 110 112 114 116 40 30 20 10 0 10 20 30 40 50 60 70 80 90 Temperature C F RC kHz 85 C 25 C 40 C 106 108 110 112 114 116 118 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V F RC kHz ...

Page 377: ...scillator Frequency vs VCC Figure 30 85 ATmega48PA Calibrated 8MHz RC Oscillator Frequency vs Temperature 85 C 25 C 40 C 7 6 7 7 7 8 7 9 8 8 1 8 2 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V F RC MHz 5 5 V 3 3 V 1 8 V 7 6 7 7 7 8 7 9 8 8 1 8 2 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 Temperature C F RC MHz ...

Page 378: ... vs OSCCAL Value 30 2 12 Current Consumption of Peripheral Units Figure 30 87 ATmega48PA ADC Current vs VCC AREF AVCC 85 C 25 C 40 C 0 2 4 6 8 10 12 14 16 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL X1 F RC MHz 85 C 25 C 40 C 0 50 100 150 200 250 300 350 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ...

Page 379: ...a48PA Analog Comparator Current vs VCC Figure 30 89 ATmega48PA AREF External Reference Current vs VCC 85 C 25 C 40 C 0 10 20 30 40 50 60 70 80 90 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA 85 C 25 C 40 C 0 20 40 60 80 100 120 140 160 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ...

Page 380: ...P Figure 30 90 ATmega48PA Brownout Detector Current vs VCC Figure 30 91 ATmega48PA Programming Current vs VCC 85 C 25 C 40 C 0 8 16 24 32 40 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA 85 C 25 C 40 C 0 1 2 3 4 5 6 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 381: ...Current vs Low Frequency 0 1 1 0MHz Figure 30 93 ATmega48PA Reset Supply Current vs Frequency 1 20MHz 5 5 V 5 0 V 4 5 V 4 0 V 3 3 V 2 7 V 1 8 V 0 0 02 0 04 0 06 0 08 0 1 0 12 0 14 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz I CC mA 5 5 V 5 0 V 4 5 V 0 0 5 1 1 5 2 2 5 0 2 4 6 8 10 12 14 16 18 20 Frequency MHz I CC mA 1 8 V 2 7 V 3 3 V 4 0 V ...

Page 382: ...racteristics 30 3 1 Active Supply Current Figure 30 95 ATmega88A Active Supply Current vs Low Frequency 0 1 1 0MHz 85 C 25 C 40 C 0 200 400 600 800 1000 1200 1400 1600 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Pulsewidth ns 5 5 V 5 0 V 4 5 V 4 0 V 3 3 V 2 7 V 1 8 V 0 0 2 0 4 0 6 0 8 1 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz I CC mA ...

Page 383: ...rrent vs Frequency 1 20MHz Figure 30 97 ATmega88A Active Supply Current vs VCC Internal RC Oscillator 128kHz 5 5 V 5 0 V 4 5 V 0 2 4 6 8 10 12 0 2 4 6 8 10 12 14 16 18 20 Frequency MHz I CC mA 1 8 V 2 7 V 3 3 V 4 0 V 85 C 25 C 40 C 0 0 03 0 06 0 09 0 12 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 384: ...ve Supply Current vs VCC Internal RC Oscillator 1MHz Figure 30 99 ATmega88A Active Supply Current vs VCC Internal RC Oscillator 8MHz 85 C 25 C 40 C 0 0 2 0 4 0 6 0 8 1 1 2 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA 85 C 25 C 40 C 0 1 2 3 4 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 385: ...Low Frequency 0 1 1 0MHz Figure 30 101 ATmega88A Idle Supply Current vs Frequency 1 20MHz 5 5 V 5 0 V 4 5 V 4 0 V 3 3 V 2 7 V 1 8 V 0 0 03 0 06 0 09 0 12 0 15 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz I CC mA 5 5 V 5 0 V 4 5 V 0 0 5 1 1 5 2 2 5 0 2 4 6 8 10 12 14 16 18 20 Frequency MHz I CC mA 4 0 V 3 3 V 2 7 V 1 8 V ...

Page 386: ...urrent vs VCC Internal RC Oscillator 128kHz Figure 30 103 ATmega88A Idle Supply Current vs VCC Internal RC Oscillator 1MHz 85 C 25 C 40 C 0 0 01 0 02 0 03 0 04 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA 85 C 25 C 40 C 0 0 05 0 1 0 15 0 2 0 25 0 3 0 35 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 387: ... 8271D AVR 05 11 ATmega48A PA 88A PA 168A PA 328 P Figure 30 104 ATmega88A Idle Supply Current vs Vcc Internal RC Oscillator 8MHz 85 C 25 C 40 C 0 0 3 0 6 0 9 1 2 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 388: ...gure 30 147 on page 410 we find that the idle current consumption is 0 027 mA at VCC 2 0V and F 1MHz The total current consumption in idle mode with TIMER1 ADC and SPI enabled gives Table 30 5 ATmega88PA Additional Current Consumption for the different I O modules absolute values PRR bit Typical numbers VCC 2V F 1MHz VCC 3V F 4MHz VCC 5V F 8MHz PRUSART0 3 0uA 21 3uA 97 9uA PRTWI 6 1uA 45 4uA 219 0...

Page 389: ...ATmega88A Power Down Supply Current vs VCC Watchdog Timer Disabled Figure 30 106 ATmega88A Power Down Supply Current vs VCC Watchdog Timer Enabled 85 C 25 C 40 C 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA 85 C 25 C 40 C 0 2 4 6 8 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ...

Page 390: ...32kHz Crystal Oscillator Running 30 3 6 Standby Supply Current Figure 30 108 ATmega88A Standby Supply Current vs Vcc Watchdog Timer Disabled 0 0 5 1 1 5 2 2 5 3 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA 85 C 25 C 40 C 0 0 02 0 04 0 06 0 08 0 1 0 12 0 14 0 16 0 18 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA 6MHz_xtal 6MHz_res 4MHz_xtal 4MHz_res 450kHz_res 2MHz_xtal 2MHz_res ...

Page 391: ... O Pin Pull up Resistor Current vs Input Voltage VCC 1 8 V Figure 30 110 ATmega88A I O Pin Pull up Resistor Current vs Input Voltage VCC 2 7 V 85 C 25 C 40 C 0 10 20 30 40 50 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 VOP V I OP uA 85 C 25 C 40 C 0 10 20 30 40 50 60 70 80 0 0 5 1 1 5 2 2 5 3 VOP V I OP uA ...

Page 392: ...up Resistor Current vs Input Voltage VCC 5 V Figure 30 112 ATmega88A Reset Pull up Resistor Current vs Reset Pin Voltage VCC 1 8 V 85 C 25 C 40 C 0 20 40 60 80 100 120 140 0 1 2 3 4 5 VOP V I OP uA 85 C 25 C 40 C 0 5 10 15 20 25 30 35 40 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 VRESET V I RESET uA ...

Page 393: ...esistor Current vs Reset Pin Voltage VCC 2 7 V Figure 30 114 ATmega88A Reset Pull up Resistor Current vs Reset Pin Voltage VCC 5 V 85 C 0 10 20 30 40 50 60 0 0 5 1 1 5 2 2 5 3 VRESET V I RESET uA 40 C 25 C 85 C 40 C 25 C 0 20 40 60 80 100 120 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 VRESET V I RESET uA ...

Page 394: ...gth Figure 30 115 ATmega88A I O Pin Output Voltage vs Sink Current VCC 3 V Figure 30 116 ATmega88A I O Pin Output Voltage vs Sink Current VCC 5 V 85 C 25 C 40 C 0 0 2 0 4 0 6 0 8 1 0 4 8 12 16 20 IOL mA V OL V 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 0 4 8 12 16 20 IOL mA V OL V ...

Page 395: ...ga88A I O Pin Output Voltage vs Source Current Vcc 3 V Figure 30 118 ATmega88A I O Pin Output Voltage vs Source Current VCC 5 V 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 3 3 5 0 4 8 12 16 20 IOH mA V OH V 85 C 25 C 40 C 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 4 8 12 16 20 IOH mA V OH V ...

Page 396: ...a88A I O Pin Input Threshold Voltage vs VCC VIH I O Pin read as 1 Figure 30 120 ATmega88A I O Pin Input Threshold Voltage vs VCC VIL I O Pin read as 0 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 3 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V ...

Page 397: ...n Input Hysteresis vs VCC Figure 30 122 ATmega88A Reset Input Threshold Voltage vs VCC VIH I O Pin read as 1 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Input Hysteresis V 85 C 25 C 40 C 0 0 3 0 6 0 9 1 2 1 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V ...

Page 398: ... Input Threshold Voltage vs VCC VIL I O Pin read as 0 Figure 30 124 ATmega88A Reset Pin Input Hysteresis vs VCC 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Input Hysteresis V ...

Page 399: ...EL is 1 8 V Figure 30 126 ATmega88A BOD Thresholds vs Temperature BODLEVEL is 2 7 V Rising Vcc Falling Vcc 1 77 1 78 1 79 1 8 1 81 1 82 1 83 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 Temperature C Threshold V Rising Vcc Falling Vcc 2 64 2 66 2 68 2 7 2 72 2 74 2 76 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 Temperature C Threshold V ...

Page 400: ...re BODLEVEL is 4 3 V Figure 30 128 ATmega88A Bandgap Voltage vs VCC Rising Vcc Falling Vcc 4 22 4 24 4 26 4 28 4 3 4 32 4 34 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 Temperature C Threshold V 85 C 25 C 40 C 1 096 1 097 1 098 1 099 1 1 1 101 1 102 1 103 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Bandgap Voltage V ...

Page 401: ...ga88A Watchdog Oscillator Frequency vs Temperature Figure 30 130 ATmega88A Watchdog Oscillator Frequency vs VCC 5 5 V 4 0 V 3 3 V 2 7 V 105 106 107 108 109 110 111 112 113 114 40 20 0 20 40 60 80 100 Temperature C F RC kHz 85 C 25 C 40 C 104 106 108 110 112 114 116 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V F RC kHz ...

Page 402: ... 8MHz RC Oscillator Frequency vs VCC Figure 30 132 ATmega88A Calibrated 8MHz RC Oscillator Frequency vs Temperature 85 C 25 C 40 C 7 6 7 7 7 8 7 9 8 8 1 8 2 8 3 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V F RC MHz 5 5 V 4 0 V 3 0 V 7 8 7 9 8 8 1 8 2 8 3 40 20 0 20 40 60 80 100 Temperature C F RC MHz ...

Page 403: ...ncy vs OSCCAL Value 30 3 12 Current Consumption of Peripheral Units Figure 30 134 ATmega88A ADC Current vs VCC AREF AVCC 85 C 25 C 40 C 0 2 4 6 8 10 12 14 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL X1 F RC MHz 85 C 25 C 40 C 0 50 100 150 200 250 300 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ...

Page 404: ...ga88A Analog Comparator Current vs VCC Figure 30 136 ATmega88A AREF External Reference Current vs VCC 85 C 25 C 40 C 0 10 20 30 40 50 60 70 80 90 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA 85 C 25 C 40 C 0 20 40 60 80 100 120 140 160 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ...

Page 405: ...Figure 30 137 ATmega88A Brownout Detector Current vs VCC Figure 30 138 ATmega88A Programming Current vs VCC 85 C 25 C 40 C 0 10 20 30 40 50 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA 85 C 25 C 40 C 0 1 2 3 4 5 6 7 8 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 406: ... Current vs Low Frequency 0 1 1 0MHz Figure 30 140 ATmega88A Reset Supply Current vs Frequency 1 20MHz 5 5 V 5 0 V 4 5 V 4 0 V 3 3 V 2 7 V 1 8 V 0 0 02 0 04 0 06 0 08 0 1 0 12 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz I CC mA 5 5 V 5 0 V 4 5 V 0 0 4 0 8 1 2 1 6 2 0 2 4 6 8 10 12 14 16 18 20 Frequency MHz I CC mA 1 8 V 2 7 V 4 0 V 3 3 V ...

Page 407: ...acteristics 30 4 1 Active Supply Current Figure 30 142 ATmega88PA Active Supply Current vs Low Frequency 0 1 1 0MHz 85 C 25 C 40 C 0 200 400 600 800 1000 1200 1400 1600 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Pulsewidth ns 5 5 V 5 0 V 4 5 V 4 0 V 3 3 V 2 7 V 1 8 V 0 0 2 0 4 0 6 0 8 1 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz I CC mA ...

Page 408: ...rrent vs Frequency 1 20MHz Figure 30 144 ATmega88PA Active Supply Current vs VCC Internal RC Oscillator 128kHz 5 5 V 5 0 V 4 5 V 0 2 4 6 8 10 12 0 2 4 6 8 10 12 14 16 18 20 Frequency MHz I CC mA 1 8 V 2 7 V 3 3 V 4 0 V 85 C 25 C 40 C 0 0 03 0 06 0 09 0 12 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 409: ...ve Supply Current vs VCC Internal RC Oscillator 1MHz Figure 30 146 ATmega88PA Active Supply Current vs VCC Internal RC Oscillator 8MHz 85 C 25 C 40 C 0 0 2 0 4 0 6 0 8 1 1 2 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA 85 C 25 C 40 C 0 1 2 3 4 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 410: ...Low Frequency 0 1 1 0MHz Figure 30 148 ATmega88PA Idle Supply Current vs Frequency 1 20MHz 5 5 V 5 0 V 4 5 V 4 0 V 3 3 V 2 7 V 1 8 V 0 0 03 0 06 0 09 0 12 0 15 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz I CC mA 5 5 V 5 0 V 4 5 V 0 0 5 1 1 5 2 2 5 0 2 4 6 8 10 12 14 16 18 20 Frequency MHz I CC mA 4 0 V 3 3 V 2 7 V 1 8 V ...

Page 411: ...urrent vs VCC Internal RC Oscillator 128kHz Figure 30 150 ATmega88PA Idle Supply Current vs VCC Internal RC Oscillator 1MHz 85 C 25 C 40 C 0 0 01 0 02 0 03 0 04 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA 85 C 25 C 40 C 0 0 05 0 1 0 15 0 2 0 25 0 3 0 35 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 412: ... 8271D AVR 05 11 ATmega48A PA 88A PA 168A PA 328 P Figure 30 151 ATmega88PA Idle Supply Current vs Vcc Internal RC Oscillator 8MHz 85 C 25 C 40 C 0 0 3 0 6 0 9 1 2 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 413: ...ge 410 we find that the idle current consumption is 0 027 mA at VCC 2 0V and F 1MHz The total current consumption in idle mode with TIMER1 ADC and SPI enabled gives Table 30 7 ATmega88PA Additional Current Consumption for the different I O modules absolute values PRR bit Typical numbers VCC 2V F 1MHz VCC 3V F 4MHz VCC 5V F 8MHz PRUSART0 3 0uA 21 3uA 97 9uA PRTWI 6 1uA 45 4uA 219 0uA PRTIM2 5 2uA 3...

Page 414: ...Tmega88PA Power Down Supply Current vs VCC Watchdog Timer Disabled Figure 30 153 ATmega88PA Power Down Supply Current vs VCC Watchdog Timer Enabled 85 C 25 C 40 C 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA 85 C 25 C 40 C 0 2 4 6 8 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ...

Page 415: ...g 30 4 6 Standby Supply Current Figure 30 155 ATmega88PA Standby Supply Current vs Vcc Watchdog Timer Disabled WATCHDOG TIMER DISABLED and 32 kHz CRYSTAL OSCILLATOR RUNNING 0 0 5 1 1 5 2 2 5 3 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA 85 C 25 C 40 C 0 0 02 0 04 0 06 0 08 0 1 0 12 0 14 0 16 0 18 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA 6MHz_xtal 6MHz_res 4MHz_xtal 4MHz_res 450kHz_res 2MHz_xtal 2MH...

Page 416: ... O Pin Pull up Resistor Current vs Input Voltage VCC 1 8 V Figure 30 157 ATmega88PA I O Pin Pull up Resistor Current vs Input Voltage VCC 2 7 V 85 C 25 C 40 C 0 10 20 30 40 50 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 VOP V I OP uA 85 C 25 C 40 C 0 10 20 30 40 50 60 70 80 0 0 5 1 1 5 2 2 5 3 VOP V I OP uA ...

Page 417: ...up Resistor Current vs Input Voltage VCC 5 V Figure 30 159 ATmega88PA Reset Pull up Resistor Current vs Reset Pin Voltage VCC 1 8 V 85 C 25 C 40 C 0 20 40 60 80 100 120 140 0 1 2 3 4 5 VOP V I OP uA 85 C 25 C 40 C 0 5 10 15 20 25 30 35 40 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 VRESET V I RESET uA ...

Page 418: ...esistor Current vs Reset Pin Voltage VCC 2 7 V Figure 30 161 ATmega88PA Reset Pull up Resistor Current vs Reset Pin Voltage VCC 5 V 85 C 0 10 20 30 40 50 60 0 0 5 1 1 5 2 2 5 3 VRESET V I RESET uA 40 C 25 C 85 C 40 C 25 C 0 20 40 60 80 100 120 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 VRESET V I RESET uA ...

Page 419: ...th Figure 30 162 ATmega88PA I O Pin Output Voltage vs Sink Current VCC 3 V Figure 30 163 ATmega88PA I O Pin Output Voltage vs Sink Current VCC 5 V 85 C 25 C 40 C 0 0 2 0 4 0 6 0 8 1 0 4 8 12 16 20 IOL mA V OL V 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 0 4 8 12 16 20 IOL mA V OL V ...

Page 420: ...a88PA I O Pin Output Voltage vs Source Current Vcc 3 V Figure 30 165 ATmega88PA I O Pin Output Voltage vs Source Current VCC 5 V 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 3 3 5 0 4 8 12 16 20 IOH mA V OH V 85 C 25 C 40 C 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 4 8 12 16 20 IOH mA V OH V ...

Page 421: ...88PA I O Pin Input Threshold Voltage vs VCC VIH I O Pin read as 1 Figure 30 167 ATmega88PA I O Pin Input Threshold Voltage vs VCC VIL I O Pin read as 0 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 3 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V ...

Page 422: ...n Input Hysteresis vs VCC Figure 30 169 ATmega88PA Reset Input Threshold Voltage vs VCC VIH I O Pin read as 1 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Input Hysteresis V 85 C 25 C 40 C 0 0 3 0 6 0 9 1 2 1 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V ...

Page 423: ... Input Threshold Voltage vs VCC VIL I O Pin read as 0 Figure 30 171 ATmega88PA Reset Pin Input Hysteresis vs VCC 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Input Hysteresis V ...

Page 424: ...EL is 1 8 V Figure 30 173 ATmega88PA BOD Thresholds vs Temperature BODLEVEL is 2 7 V Rising Vcc Falling Vcc 1 77 1 78 1 79 1 8 1 81 1 82 1 83 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 Temperature C Threshold V Rising Vcc Falling Vcc 2 64 2 66 2 68 2 7 2 72 2 74 2 76 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 Temperature C Threshold V ...

Page 425: ...re BODLEVEL is 4 3 V Figure 30 175 ATmega88PA Bandgap Voltage vs VCC Rising Vcc Falling Vcc 4 22 4 24 4 26 4 28 4 3 4 32 4 34 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 Temperature C Threshold V 85 C 25 C 40 C 1 096 1 097 1 098 1 099 1 1 1 101 1 102 1 103 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Bandgap Voltage V ...

Page 426: ...a88PA Watchdog Oscillator Frequency vs Temperature Figure 30 177 ATmega88PA Watchdog Oscillator Frequency vs VCC 5 5 V 4 0 V 3 3 V 2 7 V 105 106 107 108 109 110 111 112 113 114 40 20 0 20 40 60 80 100 Temperature C F RC kHz 85 C 25 C 40 C 104 106 108 110 112 114 116 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V F RC kHz ...

Page 427: ... 8MHz RC Oscillator Frequency vs VCC Figure 30 179 ATmega88PA Calibrated 8MHz RC Oscillator Frequency vs Temperature 85 C 25 C 40 C 7 6 7 7 7 8 7 9 8 8 1 8 2 8 3 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V F RC MHz 5 5 V 4 0 V 3 0 V 7 8 7 9 8 8 1 8 2 8 3 40 20 0 20 40 60 80 100 Temperature C F RC MHz ...

Page 428: ...ncy vs OSCCAL Value 30 4 12 Current Consumption of Peripheral Units Figure 30 181 ATmega88PA ADC Current vs VCC AREF AVCC 85 C 25 C 40 C 0 2 4 6 8 10 12 14 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL X1 F RC MHz 85 C 25 C 40 C 0 50 100 150 200 250 300 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ...

Page 429: ...a88PA Analog Comparator Current vs VCC Figure 30 183 ATmega88PA AREF External Reference Current vs VCC 85 C 25 C 40 C 0 10 20 30 40 50 60 70 80 90 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA 85 C 25 C 40 C 0 20 40 60 80 100 120 140 160 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ...

Page 430: ...igure 30 184 ATmega88PA Brownout Detector Current vs VCC Figure 30 185 ATmega88PA Programming Current vs VCC 85 C 25 C 40 C 0 10 20 30 40 50 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA 85 C 25 C 40 C 0 1 2 3 4 5 6 7 8 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 431: ... Current vs Low Frequency 0 1 1 0MHz Figure 30 187 ATmega88PA Reset Supply Current vs Frequency 1 20MHz 5 5 V 5 0 V 4 5 V 4 0 V 3 3 V 2 7 V 1 8 V 0 0 02 0 04 0 06 0 08 0 1 0 12 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz I CC mA 5 5 V 5 0 V 4 5 V 0 0 4 0 8 1 2 1 6 2 0 2 4 6 8 10 12 14 16 18 20 Frequency MHz I CC mA 1 8 V 2 7 V 4 0 V 3 3 V ...

Page 432: ...racteristics 30 5 1 Active Supply Current Figure 30 189 ATmega168A Active Supply Current vs Low Frequency 0 1 1 0MHz 85 C 25 C 40 C 0 200 400 600 800 1000 1200 1400 1600 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Pulsewidth ns 5 5 V 5 0 V 4 5 V 4 0 V 3 3 V 2 7 V 1 8 V 0 0 2 0 4 0 6 0 8 1 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz I CC mA ...

Page 433: ...nt vs Frequency 1 20MHz Figure 30 191 ATmega168A Active Supply Current vs VCC Internal RC Oscillator 128kHz 5 5 V 5 0 V 4 5 V 0 2 4 6 8 10 12 0 2 4 6 8 10 12 14 16 18 20 Frequency MHz I CC mA 1 8 V 4 0 V 3 3 V 2 7 V 85 C 25 C 40 C 0 0 03 0 06 0 09 0 12 0 15 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 434: ...ve Supply Current vs VCC Internal RC Oscillator 1MHz Figure 30 193 ATmega168A Active Supply Current vs VCC Internal RC Oscillator 8MHz 85 C 25 C 40 C 0 0 2 0 4 0 6 0 8 1 1 2 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA 25 C 40 C 0 1 2 3 4 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA 85 C ...

Page 435: ...ow Frequency 0 1 1 0MHz Figure 30 195 ATmega168A Idle Supply Current vs Frequency 1 20MHz 5 5 V 5 0 V 4 5 V 4 0 V 3 3 V 2 7 V 1 8 V 0 0 03 0 06 0 09 0 12 0 15 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz I CC mA 5 5 V 5 0 V 4 5 V 0 0 5 1 1 5 2 2 5 3 0 2 4 6 8 10 12 14 16 18 20 Frequency MHz I CC mA 1 8 V 2 7 V 4 0 V 3 3 V ...

Page 436: ... VCC Internal RC Oscillator 128kHz Figure 30 197 ATmega168A Idle Supply Current vs VCC Internal RC Oscillator 1MHz 85 C 25 C 40 C 0 0 005 0 01 0 015 0 02 0 025 0 03 0 035 0 04 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA 85 C 25 C 40 C 0 0 05 0 1 0 15 0 2 0 25 0 3 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 437: ... 8271D AVR 05 11 ATmega48A PA 88A PA 168A PA 328 P Figure 30 198 ATmega168A Idle Supply Current vs Vcc Internal RC Oscillator 8MHz 85 C 25 C 40 C 0 0 3 0 6 0 9 1 2 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 438: ...gure 30 241 on page 460 we find that the idle current consumption is 0 027 mA at VCC 2 0V and F 1MHz The total current consumption in idle mode with TIMER1 ADC and SPI enabled gives Table 30 9 ATmega168A Additional Current Consumption for the different I O modules absolute values PRR bit Typical numbers VCC 2V F 1MHz VCC 3V F 4MHz VCC 5V F 8MHz PRUSART0 2 86uA 20 3uA 52 2uA PRTWI 6 00uA 44 1uA 122...

Page 439: ... 199 ATmega168A Power Down Supply Current vs VCC Watchdog Timer Disabled Figure 30 200 ATmega168A Power Down Supply Current vs VCC Watchdog Timer Enabled 85 C 25 C 40 C 0 0 2 0 4 0 6 0 8 1 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA 85 C 25 C 40 C 0 2 4 6 8 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ...

Page 440: ... 32kHz Crystal Oscillator Running 30 5 6 Standby Supply Current Figure 30 202 ATmega168A Standby Supply Current vs Vcc Watchdog Timer Disabled 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA 6MHz_xtal 6MHz_res 4MHz_xtal 4MHz_res 450kHz_res 2MHz_xtal 2MHz_res 1MHz_res 0 0 02 0 04 0 06 0 08 0 1 0 12 0 14 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC MHz I CC mA ...

Page 441: ...O Pin Pull up Resistor Current vs Input Voltage VCC 1 8 V Figure 30 204 ATmega168A I O Pin Pull up Resistor Current vs Input Voltage VCC 2 7 V 85 C 25 C 40 C 0 10 20 30 40 50 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 2 VOP V I OP uA 85 C 25 C 40 C 0 10 20 30 40 50 60 70 80 0 0 5 1 1 5 2 2 5 3 VOP V I OP uA ...

Page 442: ...Resistor Current vs Input Voltage VCC 5 V Figure 30 206 ATmega168A Reset Pull up Resistor Current vs Reset Pin Voltage VCC 1 8 V 85 C 25 C 40 C 0 20 40 60 80 100 120 140 160 0 1 2 3 4 5 6 VOP V I OP uA 85 C 25 C 40 C 0 5 10 15 20 25 30 35 40 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 VRESET V I RESET uA ...

Page 443: ...t Pull up Resistor Current vs Reset Pin Voltage VCC 2 7 V Figure 30 208 ATmega168A Reset Pull up Resistor Current vs Reset Pin Voltage VCC 5V 85 C 0 10 20 30 40 50 60 0 0 5 1 1 5 2 2 5 3 VRESET V I RESET uA 40 C 25 C 0 20 40 60 80 100 120 0 1 2 3 4 5 VRESET V I RESET uA 85 C 40 C 25 C ...

Page 444: ...th Figure 30 209 ATmega168A I O Pin Output Voltage vs Sink Current VCC 3 V Figure 30 210 ATmega168A I O Pin Output Voltage vs Sink Current VCC 5 V 85 C 25 C 40 C 0 0 2 0 4 0 6 0 8 1 0 4 8 12 16 20 IOL mA V OL V 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 0 4 8 12 16 20 IOL mA V OL V ...

Page 445: ...1 ATmega168A I O Pin Output Voltage vs Source Current Vcc 3 V Figure 30 212 ATmega168A I O Pin Output Voltage vs Source Current VCC 5 V 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 3 3 5 0 4 8 12 16 20 IOH mA V OH V 85 C 25 C 40 C 4 4 2 4 4 4 6 4 8 5 0 4 8 12 16 20 IOH mA V OH V ...

Page 446: ...168A I O Pin Input Threshold Voltage vs VCC VIH I O Pin read as 1 Figure 30 214 ATmega168A I O Pin Input Threshold Voltage vs VCC VIL I O Pin read as 0 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 3 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V ...

Page 447: ...n Input Hysteresis vs VCC Figure 30 216 ATmega168A Reset Input Threshold Voltage vs VCC VIH I O Pin read as 1 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Input Hysteresis V 85 C 25 C 40 C 0 0 3 0 6 0 9 1 2 1 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V ...

Page 448: ...nput Threshold Voltage vs VCC VIL I O Pin read as 0 Figure 30 218 ATmega168A Reset Pin Input Hysteresis vs VCC 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Input Hysteresis V ...

Page 449: ... 1 8 V Figure 30 220 ATmega168A BOD Thresholds vs Temperature BODLEVEL is 2 7 V Rising Vcc Falling Vcc 1 72 1 74 1 76 1 78 1 8 1 82 1 84 1 86 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 Temperature C Threshold V Rising Vcc Falling Vcc 2 62 2 64 2 66 2 68 2 7 2 72 2 74 2 76 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 Temperature C Threshold V ...

Page 450: ...is 4 3 V Figure 30 222 ATmega168A Bandgap Voltage vs VCC Rising Vcc Falling Vcc 4 2 4 22 4 24 4 26 4 28 4 3 4 32 4 34 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 Temperature C Threshold V 85 C 25 C 40 C 1 115 1 117 1 119 1 121 1 123 1 125 1 127 1 129 1 131 1 133 1 135 1 5 2 2 5 3 3 5 4 4 5 5 5 5 Vcc V Bandgap Voltage V ...

Page 451: ...ega168A Watchdog Oscillator Frequency vs Temperature Figure 30 224 ATmega168A Watchdog Oscillator Frequency vs VCC 5 5 V 3 3 V 2 7 V 111 113 115 117 119 121 40 30 20 10 0 10 20 30 40 50 60 70 80 90 Temperature C F RC kHz 85 C 25 C 40 C 110 112 114 116 118 120 122 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V F RC kHz ...

Page 452: ...ator Frequency vs VCC Figure 30 226 ATmega168A Calibrated 8MHz RC Oscillator Frequency vs Temperature 85 C 25 C 40 C 7 4 7 6 7 8 8 8 2 8 4 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V F RC MHz 5 5 V 5 0 V 2 7 V 1 8 V 7 5 7 6 7 7 7 8 7 9 8 8 1 8 2 8 3 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 Temperature C F RC MHz ...

Page 453: ...cy vs OSCCAL Value 30 5 12 Current Consumption of Peripheral Units Figure 30 228 ATmega168A ADC Current vs VCC AREF AVCC 85 C 25 C 40 C 0 2 4 6 8 10 12 14 16 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL X1 F RC MHz 85 C 25 C 40 C 100 150 200 250 300 350 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ...

Page 454: ...ega168A Analog Comparator Current vs VCC Figure 30 230 ATmega168A AREF External Reference Current vs VCC 85 C 25 C 40 C 30 40 50 60 70 80 90 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA 85 C 25 C 40 C 0 20 40 60 80 100 120 140 160 180 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ...

Page 455: ...gure 30 231 ATmega168A Brownout Detector Current vs VCC Figure 30 232 ATmega168A Programming Current vs VCC 85 C 25 C 40 C 12 14 16 18 20 22 24 26 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA 85 C 25 C 40 C 0 2 4 6 8 10 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 456: ...y Current vs Low Frequency 0 1 1 0MHz Figure 30 234 ATmega168A Reset Supply Current vs Frequency 1 20MHz 5 5 V 5 0 V 4 5 V 4 0 V 3 3 V 2 7 V 1 8 V 0 0 02 0 04 0 06 0 08 0 1 0 12 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz I CC mA 5 5 V 5 0 V 4 5 V 0 0 5 1 1 5 2 2 5 0 2 4 6 8 10 12 14 16 18 20 Frequency MHz I CC mA 1 8 V 2 7 V 3 3 V 4 0 V ...

Page 457: ...haracteristics 30 6 1 Active Supply Current Figure 30 236 ATmega168PA Active Supply Current vs Low Frequency 0 1 1 0MHz 85 C 25 C 40 C 0 250 500 750 1000 1250 1500 1750 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Pulsewidth ns 5 5 V 5 0 V 4 5 V 4 0 V 3 3 V 2 7 V 1 8 V 0 0 2 0 4 0 6 0 8 1 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz I CC mA ...

Page 458: ...nt vs Frequency 1 20MHz Figure 30 238 ATmega168PA Active Supply Current vs VCC Internal RC Oscillator 128kHz 5 5 V 5 0 V 4 5 V 0 2 4 6 8 10 12 0 2 4 6 8 10 12 14 16 18 20 Frequency MHz I CC mA 1 8 V 4 0 V 3 3 V 2 7 V 85 C 25 C 40 C 0 0 03 0 06 0 09 0 12 0 15 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 459: ...ve Supply Current vs VCC Internal RC Oscillator 1MHz Figure 30 240 ATmega168PA Active Supply Current vs VCC Internal RC Oscillator 8MHz 85 C 25 C 40 C 0 0 2 0 4 0 6 0 8 1 1 2 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA 25 C 40 C 0 1 2 3 4 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA 85 C ...

Page 460: ...ow Frequency 0 1 1 0MHz Figure 30 242 ATmega168PA Idle Supply Current vs Frequency 1 20MHz 5 5 V 5 0 V 4 5 V 4 0 V 3 3 V 2 7 V 1 8 V 0 0 03 0 06 0 09 0 12 0 15 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz I CC mA 5 5 V 5 0 V 4 5 V 0 0 5 1 1 5 2 2 5 3 0 2 4 6 8 10 12 14 16 18 20 Frequency MHz I CC mA 1 8 V 2 7 V 4 0 V 3 3 V ...

Page 461: ... VCC Internal RC Oscillator 128kHz Figure 30 244 ATmega168PA Idle Supply Current vs VCC Internal RC Oscillator 1MHz 85 C 25 C 40 C 0 0 005 0 01 0 015 0 02 0 025 0 03 0 035 0 04 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA 85 C 25 C 40 C 0 0 05 0 1 0 15 0 2 0 25 0 3 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 462: ...8271D AVR 05 11 ATmega48A PA 88A PA 168A PA 328 P Figure 30 245 ATmega168PA Idle Supply Current vs Vcc Internal RC Oscillator 8MHz 85 C 25 C 40 C 0 0 3 0 6 0 9 1 2 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 463: ...ure 30 241 on page 460 we find that the idle current consumption is 0 027 mA at VCC 2 0V and F 1MHz The total current consumption in idle mode with TIMER1 ADC and SPI enabled gives Table 30 11 ATmega168PA Additional Current Consumption for the different I O modules absolute values PRR bit Typical numbers VCC 2V F 1MHz VCC 3V F 4MHz VCC 5V F 8MHz PRUSART0 2 86uA 20 3uA 52 2uA PRTWI 6 00uA 44 1uA 12...

Page 464: ...246 ATmega168PA Power Down Supply Current vs VCC Watchdog Timer Disabled Figure 30 247 ATmega168PA Power Down Supply Current vs VCC Watchdog Timer Enabled 85 C 25 C 40 C 0 0 2 0 4 0 6 0 8 1 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA 85 C 25 C 40 C 0 2 4 6 8 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ...

Page 465: ... 32kHz Crystal Oscillator Running 30 6 6 Standby Supply Current Figure 30 249 ATmega168PA Standby Supply Current vs Vcc Watchdog Timer Disabled 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA 6MHz_xtal 6MHz_res 4MHz_xtal 4MHz_res 450kHz_res 2MHz_xtal 2MHz_res 1MHz_res 0 0 02 0 04 0 06 0 08 0 1 0 12 0 14 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC MHz I CC mA ...

Page 466: ...O Pin Pull up Resistor Current vs Input Voltage VCC 1 8 V Figure 30 251 ATmega168PA I O Pin Pull up Resistor Current vs Input Voltage VCC 2 7 V 85 C 25 C 40 C 0 10 20 30 40 50 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 2 VOP V I OP uA 85 C 25 C 40 C 0 10 20 30 40 50 60 70 80 0 0 5 1 1 5 2 2 5 3 VOP V I OP uA ...

Page 467: ...Resistor Current vs Input Voltage VCC 5 V Figure 30 253 ATmega168PA Reset Pull up Resistor Current vs Reset Pin Voltage VCC 1 8 V 85 C 25 C 40 C 0 20 40 60 80 100 120 140 160 0 1 2 3 4 5 6 VOP V I OP uA 85 C 25 C 40 C 0 5 10 15 20 25 30 35 40 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 VRESET V I RESET uA ...

Page 468: ...t Pull up Resistor Current vs Reset Pin Voltage VCC 2 7 V Figure 30 255 ATmega168PA Reset Pull up Resistor Current vs Reset Pin Voltage VCC 5V 85 C 0 10 20 30 40 50 60 0 0 5 1 1 5 2 2 5 3 VRESET V I RESET uA 40 C 25 C 0 20 40 60 80 100 120 0 1 2 3 4 5 VRESET V I RESET uA 85 C 40 C 25 C ...

Page 469: ...h Figure 30 256 ATmega168PA I O Pin Output Voltage vs Sink Current VCC 3 V Figure 30 257 ATmega168PA I O Pin Output Voltage vs Sink Current VCC 5 V 85 C 25 C 40 C 0 0 2 0 4 0 6 0 8 1 0 4 8 12 16 20 IOL mA V OL V 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 0 4 8 12 16 20 IOL mA V OL V ...

Page 470: ... ATmega168PA I O Pin Output Voltage vs Source Current Vcc 3 V Figure 30 259 ATmega168PA I O Pin Output Voltage vs Source Current VCC 5 V 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 3 3 5 0 4 8 12 16 20 IOH mA V OH V 85 C 25 C 40 C 4 4 2 4 4 4 6 4 8 5 0 4 8 12 16 20 IOH mA V OH V ...

Page 471: ...68PA I O Pin Input Threshold Voltage vs VCC VIH I O Pin read as 1 Figure 30 261 ATmega168PA I O Pin Input Threshold Voltage vs VCC VIL I O Pin read as 0 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 3 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V ...

Page 472: ...n Input Hysteresis vs VCC Figure 30 263 ATmega168PA Reset Input Threshold Voltage vs VCC VIH I O Pin read as 1 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Input Hysteresis V 85 C 25 C 40 C 0 0 3 0 6 0 9 1 2 1 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V ...

Page 473: ...nput Threshold Voltage vs VCC VIL I O Pin read as 0 Figure 30 265 ATmega168PA Reset Pin Input Hysteresis vs VCC 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Input Hysteresis V ...

Page 474: ... 1 8 V Figure 30 267 ATmega168PA BOD Thresholds vs Temperature BODLEVEL is 2 7 V Rising Vcc Falling Vcc 1 72 1 74 1 76 1 78 1 8 1 82 1 84 1 86 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 Temperature C Threshold V Rising Vcc Falling Vcc 2 62 2 64 2 66 2 68 2 7 2 72 2 74 2 76 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 Temperature C Threshold V ...

Page 475: ...is 4 3 V Figure 30 269 ATmega168PA Bandgap Voltage vs VCC Rising Vcc Falling Vcc 4 2 4 22 4 24 4 26 4 28 4 3 4 32 4 34 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 Temperature C Threshold V 85 C 25 C 40 C 1 115 1 117 1 119 1 121 1 123 1 125 1 127 1 129 1 131 1 133 1 135 1 5 2 2 5 3 3 5 4 4 5 5 5 5 Vcc V Bandgap Voltage V ...

Page 476: ...ga168PA Watchdog Oscillator Frequency vs Temperature Figure 30 271 ATmega168PA Watchdog Oscillator Frequency vs VCC 5 5 V 3 3 V 2 7 V 111 113 115 117 119 121 40 30 20 10 0 10 20 30 40 50 60 70 80 90 Temperature C F RC kHz 85 C 25 C 40 C 110 112 114 116 118 120 122 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V F RC kHz ...

Page 477: ...ator Frequency vs VCC Figure 30 273 ATmega168PA Calibrated 8MHz RC Oscillator Frequency vs Temperature 85 C 25 C 40 C 7 4 7 6 7 8 8 8 2 8 4 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V F RC MHz 5 5 V 5 0 V 2 7 V 1 8 V 7 5 7 6 7 7 7 8 7 9 8 8 1 8 2 8 3 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 Temperature C F RC MHz ...

Page 478: ...cy vs OSCCAL Value 30 6 12 Current Consumption of Peripheral Units Figure 30 275 ATmega168PA ADC Current vs VCC AREF AVCC 85 C 25 C 40 C 0 2 4 6 8 10 12 14 16 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL X1 F RC MHz 85 C 25 C 40 C 100 150 200 250 300 350 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ...

Page 479: ...ga168PA Analog Comparator Current vs VCC Figure 30 277 ATmega168PA AREF External Reference Current vs VCC 85 C 25 C 40 C 30 40 50 60 70 80 90 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA 85 C 25 C 40 C 0 20 40 60 80 100 120 140 160 180 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ...

Page 480: ...ure 30 278 ATmega168PA Brownout Detector Current vs VCC Figure 30 279 ATmega168PA Programming Current vs VCC 85 C 25 C 40 C 12 14 16 18 20 22 24 26 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA 85 C 25 C 40 C 0 2 4 6 8 10 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 481: ...y Current vs Low Frequency 0 1 1 0MHz Figure 30 281 ATmega168PA Reset Supply Current vs Frequency 1 20MHz 5 5 V 5 0 V 4 5 V 4 0 V 3 3 V 2 7 V 1 8 V 0 0 02 0 04 0 06 0 08 0 1 0 12 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz I CC mA 5 5 V 5 0 V 4 5 V 0 0 5 1 1 5 2 2 5 0 2 4 6 8 10 12 14 16 18 20 Frequency MHz I CC mA 1 8 V 2 7 V 3 3 V 4 0 V ...

Page 482: ...racteristics 30 7 1 Active Supply Current Figure 30 283 ATmega328 Active Supply Current vs Low Frequency 0 1 1 0MHz 85 C 25 C 40 C 0 250 500 750 1000 1250 1500 1750 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Pulsewidth ns 5 5 V 5 0 V 4 5 V 4 0 V 3 3 V 2 7 V 1 8 V 0 0 2 0 4 0 6 0 8 1 1 2 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz I CC mA ...

Page 483: ...ent vs Frequency 1 20MHz Figure 30 285 ATmega328 Active Supply Current vs VCC Internal RC Oscillator 128kHz 5 5 V 5 0 V 4 5 V 0 2 4 6 8 10 12 14 0 2 4 6 8 10 12 14 16 18 20 Frequency MHz I CC mA 1 8 V 2 7 V 3 3 V 4 0 V 85 C 25 C 40 C 0 0 04 0 08 0 12 0 16 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 484: ...pply Current vs VCC Internal RC Oscillator 1MHz Figure 30 287 ATmega328 Active Supply Current vs VCC Internal RC Oscillator 8MHz 85 C 25 C 40 C 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA 85 C 25 C 40 C 0 1 2 3 4 5 6 7 8 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 485: ...Frequency 0 1 1 0MHz Figure 30 289 ATmega328 Idle Supply Current vs Frequency 1 20MHz 5 5 V 5 0 V 4 5 V 4 0 V 3 3 V 2 7 V 1 8 V 0 0 04 0 08 0 12 0 16 0 2 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz I CC mA 5 5 V 5 0 V 4 5 V 0 0 5 1 1 5 2 2 5 3 3 5 4 0 2 4 6 8 10 12 14 16 18 20 Frequency MHz I CC mA 1 8 V 2 7 V 3 3 V 4 0 V ...

Page 486: ...vs VCC Internal RC Oscillator 128kHz Figure 30 291 ATmega328 Idle Supply Current vs VCC Internal RC Oscillator 1MHz 85 C 25 C 40 C 0 0 01 0 02 0 03 0 04 0 05 0 06 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA 85 C 25 C 40 C 0 0 05 0 1 0 15 0 2 0 25 0 3 0 35 0 4 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 487: ...controlled by the Power Reduction Register See Power Reduction Register on page 43 for details 85 C 25 C 40 C 0 0 4 0 8 1 2 1 6 2 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA Table 30 13 ATmega328 Additional Current Consumption for the different I O modules abso lute values PRR bit Typical numbers VCC 2V F 1MHz VCC 3V F 4MHz VCC 5V F 8MHz PRUSART0 3 20 µA 22 17 µA 100 25 µA PRTWI 7 34 µA 46 55 µA 199...

Page 488: ... 30 336 on page 510 we find that the idle current consumption is 0 055 mA at VCC 2 0V and F 1MHz The total current consumption in idle mode with TIMER1 ADC and SPI enabled gives Table 30 14 ATmega328 Additional Current Consumption percentage in Active and Idle mode PRR bit Additional Current consumption compared to Active with external clock see Figure 30 330 on page 507 and Figure 30 331 on page ...

Page 489: ...mega328 Power Down Supply Current vs VCC Watchdog Timer Disabled Figure 30 294 ATmega328 Power Down Supply Current vs VCC Watchdog Timer Enabled 85 C 25 C 40 C 0 0 2 0 4 0 6 0 8 1 1 2 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA 85 C 25 C 40 C 0 1 2 3 4 5 6 7 8 9 10 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ...

Page 490: ...nd 32kHz Crystal Oscillator Running 30 7 6 Standby Supply Current Figure 30 296 ATmega328 Standby Supply Current vs Vcc Watchdog Timer Disabled 25 C 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 2 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA 6MHz_xta 6MHz_re 4MHz_xta 4MHz_re 2MHz_xta 2MHz_re 1MHz_re 0 0 02 0 04 0 06 0 08 0 1 0 12 0 14 0 16 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 491: ...in Pull up Resistor Current vs Input Voltage VCC 1 8 V Figure 30 298 ATmega328 I O Pin Pull up Resistor Current vs Input Voltage VCC 2 7 V 85 C 25 C 40 C 0 10 20 30 40 50 60 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 2 VOP V I OP uA 85 C 25 C 40 C 0 10 20 30 40 50 60 70 80 90 0 0 5 1 1 5 2 2 5 3 VOP V I OP uA ...

Page 492: ...esistor Current vs Input Voltage VCC 5 V Figure 30 300 ATmega328 Reset Pull up Resistor Current vs Reset Pin Voltage VCC 1 8 V 0 20 40 60 80 100 120 140 160 0 1 2 3 4 5 6 VOP V I OP uA 85 C 25 C 40 C 0 5 10 15 20 25 30 35 40 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 2 VRESET V I RESET uA 85 C 25 C 40 C ...

Page 493: ...ull up Resistor Current vs Reset Pin Voltage VCC 2 7 V Figure 30 302 ATmega328 Reset Pull up Resistor Current vs Reset Pin Voltage VCC 5 V 0 10 20 30 40 50 60 70 0 0 5 1 1 5 2 2 5 3 VRESET V I RESET uA 85 C 25 C 40 C 0 20 40 60 80 100 120 0 1 2 3 4 5 6 VRESET V I RESET uA 85 C 25 C 40 C ...

Page 494: ...th Figure 30 303 ATmega328 I O Pin Output Voltage vs Sink Current VCC 3 V Figure 30 304 ATmega328 I O Pin Output Voltage vs Sink Current VCC 5 V 85 C 25 C 40 C 0 0 2 0 4 0 6 0 8 1 0 5 10 15 20 25 IOL mA V OL V 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 0 5 10 15 20 25 IOL mA V OL V ...

Page 495: ...age vs Source Current Vcc 3 V Figure 30 306 ATmega328 I O Pin Output Voltage vs Source Current VCC 5 V 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 3 3 5 0 5 10 15 20 25 IOH mA V OH V I O PIN OUTPUT VOLTAGE vs SOURCE CURRENT VCC 5V 85 C 25 C 40 C 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 5 1 0 5 10 15 20 25 IOH mA V OH V ...

Page 496: ...age vs VCC VIH I O Pin read as 1 Figure 30 308 ATmega328 I O Pin Input Threshold Voltage vs VCC VIL I O Pin read as 0 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 3 3 5 4 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V I O PIN INPUT THRESHOLD VOLTAGE vs VCC VIL IO PIN READ AS 0 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V ...

Page 497: ...is vs VCC Figure 30 310 ATmega328 Reset Input Threshold Voltage vs VCC VIH I O Pin read as 1 I O PIN INPUT HYSTERESIS vs VCC 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Input Hysteresis V 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V ...

Page 498: ...nput Threshold Voltage vs VCC VIL I O Pin read as 0 Figure 30 312 ATmega328 Reset Pin Input Hysteresis vs VCC 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Input Hysteresis V ...

Page 499: ...8 BOD Thresholds vs Temperature BODLEVEL is 1 8 V Figure 30 314 ATmega328 BOD Thresholds vs Temperature BODLEVEL is 2 7 V 1 0 1 75 1 77 1 79 1 81 1 83 1 85 60 40 20 0 20 40 60 80 100 Temperature C Threshold V 1 0 2 66 2 68 2 7 2 72 2 74 2 76 2 78 60 40 20 0 20 40 60 80 100 Temperature C Threshold V ...

Page 500: ...D Thresholds vs Temperature BODLEVEL is 4 3 V Figure 30 316 ATmega328 Bandgap Voltage vs VCC 1 0 4 25 4 3 4 35 4 4 60 40 20 0 20 40 60 80 100 Temperature C Threshold V 85 C 25 C 40 C 1 124 1 126 1 128 1 13 1 132 1 134 1 136 1 138 1 5 2 2 5 3 3 5 4 4 5 5 5 5 Vcc V Bandgap Voltage V ...

Page 501: ...8 Watchdog Oscillator Frequency vs Temperature Figure 30 318 ATmega328 Watchdog Oscillator Frequency vs VCC 5 5 V 4 0 V 3 3 V 2 7 V 109 110 111 112 113 114 115 116 117 118 119 60 40 20 0 20 40 60 80 100 Temperature C F RC kHz 85 C 25 C 40 C 1 5 2 2 5 3 3 5 4 4 5 5 5 5 V F RC kHz 108 110 112 114 116 118 120 VCC ...

Page 502: ...C Figure 30 320 ATmega328 Calibrated 8MHz RC Oscillator Frequency vs Temperature CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs VCC 85 C 25 C 40 C 7 4 7 6 7 8 8 8 2 8 4 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V F RC MHz 5 0 V 3 0 V 7 6 7 7 7 8 7 9 8 8 1 8 2 8 3 8 4 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 Temperature C F RC MHz ...

Page 503: ... vs OSCCAL Value 30 7 12 Current Consumption of Peripheral Units Figure 30 322 ATmega328 ADC Current vs VCC AREF AVCC 85 C 25 C 40 C 0 2 4 6 8 10 12 14 16 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL X1 F RC MHz 85 C 25 C 40 C 0 50 100 150 200 250 300 350 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ...

Page 504: ...ega328 Analog Comparator Current vs VCC Figure 30 324 ATmega328 AREF External Reference Current vs VCC 85 C 25 C 40 C 0 20 40 60 80 100 120 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA 85 C 25 C 40 C 0 20 40 60 80 100 120 140 160 180 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ...

Page 505: ...re 30 325 ATmega328 Brownout Detector Current vs VCC Figure 30 326 ATmega328 Programming Current vs VCC 85 C 25 C 40 C 0 5 10 15 20 25 30 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA 85 C 25 C 40 C 0 1 2 3 4 5 6 7 8 9 10 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 506: ...t Supply Current vs Low Frequency 0 1 1 0MHz Figure 30 328 ATmega328 Reset Supply Current vs Frequency 1 20MHz 5 5 V 5 0 V 4 5 V 4 0 V 3 3 V 2 7 V 1 8 V 0 0 05 0 1 0 15 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz I CC mA 5 5 V 5 0 V 4 5 V 0 0 5 1 1 5 2 2 5 3 0 2 4 6 8 10 12 14 16 18 20 Frequency MHz I CC mA 1 8 V 2 7 V 3 3 V 4 0 V ...

Page 507: ...ristics 30 8 1 Active Supply Current Figure 30 330 ATmega328P Active Supply Current vs Low Frequency 0 1 1 0MHz 85 C 25 C 40 C 0 200 400 600 800 1000 1200 1400 1600 1800 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Pulsewidth ns 5 5 V 5 0 V 4 5 V 4 0 V 3 3 V 2 7 V 1 8 V 0 0 2 0 4 0 6 0 8 1 1 2 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz I CC mA ...

Page 508: ...ent vs Frequency 1 20MHz Figure 30 332 ATmega328P Active Supply Current vs VCC Internal RC Oscillator 128kHz 5 5 V 5 0 V 4 5 V 0 2 4 6 8 10 12 14 0 2 4 6 8 10 12 14 16 18 20 Frequency MHz I CC mA 1 8 V 2 7 V 3 3 V 4 0 V 85 C 25 C 40 C 0 0 04 0 08 0 12 0 16 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 509: ...pply Current vs VCC Internal RC Oscillator 1MHz Figure 30 334 ATmega328P Active Supply Current vs VCC Internal RC Oscillator 8MHz 85 C 25 C 40 C 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA 85 C 25 C 40 C 0 1 2 3 4 5 6 7 8 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 510: ...Frequency 0 1 1 0MHz Figure 30 336 ATmega328P Idle Supply Current vs Frequency 1 20MHz 5 5 V 5 0 V 4 5 V 4 0 V 3 3 V 2 7 V 1 8 V 0 0 04 0 08 0 12 0 16 0 2 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz I CC mA 5 5 V 5 0 V 4 5 V 0 0 5 1 1 5 2 2 5 3 3 5 4 0 2 4 6 8 10 12 14 16 18 20 Frequency MHz I CC mA 1 8 V 2 7 V 3 3 V 4 0 V ...

Page 511: ...vs VCC Internal RC Oscillator 128kHz Figure 30 338 ATmega328P Idle Supply Current vs VCC Internal RC Oscillator 1MHz 85 C 25 C 40 C 0 0 01 0 02 0 03 0 04 0 05 0 06 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA 85 C 25 C 40 C 0 0 05 0 1 0 15 0 2 0 25 0 3 0 35 0 4 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 512: ... controlled by the Power Reduction Register See Power Reduction Register on page 43 for details 85 C 25 C 40 C 0 0 4 0 8 1 2 1 6 2 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA Table 30 15 ATmega328P Additional Current Consumption for the different I O modules absolute values PRR bit Typical numbers VCC 2V F 1MHz VCC 3V F 4MHz VCC 5V F 8MHz PRUSART0 3 20 µA 22 17 µA 100 25 µA PRTWI 7 34 µA 46 55 µA 19...

Page 513: ...30 336 on page 510 we find that the idle current consumption is 0 055 mA at VCC 2 0V and F 1MHz The total current consumption in idle mode with TIMER1 ADC and SPI enabled gives Table 30 16 ATmega328P Additional Current Consumption percentage in Active and Idle mode PRR bit Additional Current consumption compared to Active with external clock see Figure 30 330 on page 507 and Figure 30 331 on page ...

Page 514: ...ega328P Power Down Supply Current vs VCC Watchdog Timer Disabled Figure 30 341 ATmega328P Power Down Supply Current vs VCC Watchdog Timer Enabled 85 C 25 C 40 C 0 0 2 0 4 0 6 0 8 1 1 2 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA 85 C 25 C 40 C 0 1 2 3 4 5 6 7 8 9 10 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ...

Page 515: ...32kHz Crystal Oscillator Running 30 8 6 Standby Supply Current Figure 30 343 ATmega328P Standby Supply Current vs Vcc Watchdog Timer Disabled 25 C 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 2 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA 6MHz_xtal 6MHz_res 4MHz_xtal 4MHz_res 2MHz_xtal 2MHz_res 1MHz_res 0 0 02 0 04 0 06 0 08 0 1 0 12 0 14 0 16 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 516: ...in Pull up Resistor Current vs Input Voltage VCC 1 8 V Figure 30 345 ATmega328P I O Pin Pull up Resistor Current vs Input Voltage VCC 2 7 V 85 C 25 C 40 C 0 10 20 30 40 50 60 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 2 VOP V I OP uA 85 C 25 C 40 C 0 10 20 30 40 50 60 70 80 90 0 0 5 1 1 5 2 2 5 3 VOP V I OP uA ...

Page 517: ...esistor Current vs Input Voltage VCC 5 V Figure 30 347 ATmega328P Reset Pull up Resistor Current vs Reset Pin Voltage VCC 1 8 V 0 20 40 60 80 100 120 140 160 0 1 2 3 4 5 6 VOP V I OP uA 85 C 25 C 40 C 0 5 10 15 20 25 30 35 40 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 2 VRESET V I RESET uA 85 C 25 C 40 C ...

Page 518: ...ull up Resistor Current vs Reset Pin Voltage VCC 2 7 V Figure 30 349 ATmega328P Reset Pull up Resistor Current vs Reset Pin Voltage VCC 5 V 0 10 20 30 40 50 60 70 0 0 5 1 1 5 2 2 5 3 VRESET V I RESET uA 85 C 25 C 40 C 0 20 40 60 80 100 120 0 1 2 3 4 5 6 VRESET V I RESET uA 85 C 25 C 40 C ...

Page 519: ...h Figure 30 350 ATmega328P I O Pin Output Voltage vs Sink Current VCC 3 V Figure 30 351 ATmega328P I O Pin Output Voltage vs Sink Current VCC 5 V 85 C 25 C 40 C 0 0 2 0 4 0 6 0 8 1 0 5 10 15 20 25 IOL mA V OL V 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 0 5 10 15 20 25 IOL mA V OL V ...

Page 520: ...328P I O Pin Output Voltage vs Source Current Vcc 3 V Figure 30 353 ATmega328P I O Pin Output Voltage vs Source Current VCC 5 V 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 3 3 5 0 5 10 15 20 25 IOH mA V OH V 85 C 25 C 40 C 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 5 1 0 5 10 15 20 25 IOH mA V OH V ...

Page 521: ...P I O Pin Input Threshold Voltage vs VCC VIH I O Pin read as 1 Figure 30 355 ATmega328P I O Pin Input Threshold Voltage vs VCC VIL I O Pin read as 0 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 3 3 5 4 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V ...

Page 522: ...n Input Hysteresis vs VCC Figure 30 357 ATmega328P Reset Input Threshold Voltage vs VCC VIH I O Pin read as 1 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Input Hysteresis V 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V ...

Page 523: ...nput Threshold Voltage vs VCC VIL I O Pin read as 0 Figure 30 359 ATmega328P Reset Pin Input Hysteresis vs VCC 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Input Hysteresis V ...

Page 524: ...P BOD Thresholds vs Temperature BODLEVEL is 1 8 V Figure 30 361 ATmega328P BOD Thresholds vs Temperature BODLEVEL is 2 7 V 1 0 1 75 1 77 1 79 1 81 1 83 1 85 60 40 20 0 20 40 60 80 100 Temperature C Threshold V 1 0 2 66 2 68 2 7 2 72 2 74 2 76 2 78 60 40 20 0 20 40 60 80 100 Temperature C Threshold V ...

Page 525: ...D Thresholds vs Temperature BODLEVEL is 4 3 V Figure 30 363 ATmega328P Bandgap Voltage vs VCC 1 0 4 25 4 3 4 35 4 4 60 40 20 0 20 40 60 80 100 Temperature C Threshold V 85 C 25 C 40 C 1 124 1 126 1 128 1 13 1 132 1 134 1 136 1 138 1 5 2 2 5 3 3 5 4 4 5 5 5 5 Vcc V Bandgap Voltage V ...

Page 526: ...P Watchdog Oscillator Frequency vs Temperature Figure 30 365 ATmega328P Watchdog Oscillator Frequency vs VCC 5 5 V 4 0 V 3 3 V 2 7 V 109 110 111 112 113 114 115 116 117 118 119 60 40 20 0 20 40 60 80 100 Temperature C F RC kHz 85 C 25 C 40 C 1 5 2 2 5 3 3 5 4 4 5 5 5 5 V F RC kHz 108 110 112 114 116 118 120 VCC ...

Page 527: ...cillator Frequency vs VCC Figure 30 367 ATmega328P Calibrated 8MHz RC Oscillator Frequency vs Temperature 85 C 25 C 40 C 7 4 7 6 7 8 8 8 2 8 4 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V F RC MHz 5 0 V 3 0 V 7 6 7 7 7 8 7 9 8 8 1 8 2 8 3 8 4 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 Temperature C F RC MHz ...

Page 528: ... vs OSCCAL Value 30 8 12 Current Consumption of Peripheral Units Figure 30 369 ATmega328P ADC Current vs VCC AREF AVCC 85 C 25 C 40 C 0 2 4 6 8 10 12 14 16 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL X1 F RC MHz 85 C 25 C 40 C 0 50 100 150 200 250 300 350 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ...

Page 529: ...ga328P Analog Comparator Current vs VCC Figure 30 371 ATmega328P AREF External Reference Current vs VCC 85 C 25 C 40 C 0 20 40 60 80 100 120 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA 85 C 25 C 40 C 0 20 40 60 80 100 120 140 160 180 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ...

Page 530: ...e 30 372 ATmega328P Brownout Detector Current vs VCC Figure 30 373 ATmega328P Programming Current vs VCC 85 C 25 C 40 C 0 5 10 15 20 25 30 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA 85 C 25 C 40 C 0 1 2 3 4 5 6 7 8 9 10 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 531: ...t Supply Current vs Low Frequency 0 1 1 0MHz Figure 30 375 ATmega328P Reset Supply Current vs Frequency 1 20MHz 5 5 V 5 0 V 4 5 V 4 0 V 3 3 V 2 7 V 1 8 V 0 0 05 0 1 0 15 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz I CC mA 5 5 V 5 0 V 4 5 V 0 0 5 1 1 5 2 2 5 3 0 2 4 6 8 10 12 14 16 18 20 Frequency MHz I CC mA 1 8 V 2 7 V 3 3 V 4 0 V ...

Page 532: ...D AVR 05 11 ATmega48A PA 88A PA 168A PA 328 P Figure 30 376 ATmega328P Minimum Reset Pulse width vs VCC 85 C 25 C 40 C 0 200 400 600 800 1000 1200 1400 1600 1800 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Pulsewidth ns ...

Page 533: ...0xE2 Reserved 0xE1 Reserved 0xE0 Reserved 0xDF Reserved 0xDE Reserved 0xDD Reserved 0xDC Reserved 0xDB Reserved 0xDA Reserved 0xD9 Reserved 0xD8 Reserved 0xD7 Reserved 0xD6 Reserved 0xD5 Reserved 0xD4 Reserved 0xD3 Reserved 0xD2 Reserved 0xD1 Reserved 0xD0 Reserved 0xCF Reserved 0xCE Reserved 0xCD Reserved 0xCC Reserved 0xCB Reserved 0xCA Reserved 0xC9 Reserved 0xC8 Reserved 0xC7 Reserved 0xC6 UDR...

Page 534: ...ved 0xA2 Reserved 0xA1 Reserved 0xA0 Reserved 0x9F Reserved 0x9E Reserved 0x9D Reserved 0x9C Reserved 0x9B Reserved 0x9A Reserved 0x99 Reserved 0x98 Reserved 0x97 Reserved 0x96 Reserved 0x95 Reserved 0x94 Reserved 0x93 Reserved 0x92 Reserved 0x91 Reserved 0x90 Reserved 0x8F Reserved 0x8E Reserved 0x8D Reserved 0x8C Reserved 0x8B OCR1BH Timer Counter1 Output Compare Register B High Byte 140 0x8A OC...

Page 535: ...4 SP3 SP2 SP1 SP0 13 0x3C 0x5C Reserved 0x3B 0x5B Reserved 0x3A 0x5A Reserved 0x39 0x59 Reserved 0x38 0x58 Reserved 0x37 0x57 SPMCSR SPMIE RWWSB 5 RWWSRE 5 BLBSET PGWRT PGERS SELFPRGEN 295 0x36 0x56 Reserved 0x35 0x55 MCUCR BODS 6 BODSE 6 PUD IVSEL IVCE 46 70 94 0x34 0x54 MCUSR WDRF BORF EXTRF PORF 56 0x33 0x53 SMCR SM2 SM1 SM0 SE 41 0x32 0x52 Reserved 0x31 0x51 Reserved 0x30 0x50 ACSR ACD ACBG AC...

Page 536: ... For the Extended I O space from 0x60 0xFF in SRAM only the ST STS STD and LD LDS LDD instructions can be used 5 Only valid for ATmega88A 88PA 168A 168PA 328 328P 6 BODS and BODSE only available for picoPower devices ATmega48PA 88PA 168PA 328P 0x1B 0x3B PCIFR PCIF2 PCIF1 PCIF0 0x1A 0x3A Reserved 0x19 0x39 Reserved 0x18 0x38 Reserved 0x17 0x37 TIFR2 OCF2B OCF2A TOV2 165 0x16 0x36 TIFR1 ICF1 OCF1B O...

Page 537: ...P Indirect Jump to Z PC Z None 2 JMP 1 k Direct Jump PC k None 3 RCALL k Relative Subroutine Call PC PC k 1 None 3 ICALL Indirect Call to Z PC Z None 3 CALL 1 k Direct Subroutine Call PC k None 4 RET Subroutine Return PC STACK None 4 RETI Interrupt Return PC STACK I 4 CPSE Rd Rr Compare Skip if Equal if Rd Rr PC PC 2 or 3 None 1 2 3 CP Rd Rr Compare Rd Rr Z N V C H 1 CPC Rd Rr Compare with Carry R...

Page 538: ...ve Between Registers Rd Rr None 1 MOVW Rd Rr Copy Register Word Rd 1 Rd Rr 1 Rr None 1 LDI Rd K Load Immediate Rd K None 1 LD Rd X Load Indirect Rd X None 2 LD Rd X Load Indirect and Post Inc Rd X X X 1 None 2 LD Rd X Load Indirect and Pre Dec X X 1 Rd X None 2 LD Rd Y Load Indirect Rd Y None 2 LD Rd Y Load Indirect and Post Inc Rd Y Y Y 1 None 2 LD Rd Y Load Indirect and Pre Dec Y Y 1 Rd Y None 2...

Page 539: ...ATmega328P POP Rd Pop Register from Stack Rd STACK None 2 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep see specific descr for Sleep function None 1 WDR Watchdog Reset see specific descr for WDR timer None 1 BREAK Break For On chip Debug Only None N A Mnemonics Operands Description Operation Flags Clocks ...

Page 540: ...ring Code 2 Package 1 Operational Range 20 3 1 8 5 5 ATmega48A AU ATmega48A AUR 5 ATmega48A CCU ATmega48A CCUR 5 ATmega48A MMH 4 ATmega48A MMHR 4 5 ATmega48A MU ATmega48A MUR 5 ATmega48A PU 32A 32A 32CC1 32CC1 28M1 28M1 32M1 A 32M1 A 28P3 Industrial 40 C to 85 C Package Type 32A 32 lead Thin 1 0 mm Plastic Quad Flat Package TQFP 32CC1 32 ball 4 x 4 x 0 6 mm package ball pitch 0 5 mm Ultra Thin Fin...

Page 541: ...Tmega48PA CCUR 5 ATmega48PA MMH 4 ATmega48PA MMHR 4 5 ATmega48PA MU ATmega48PA MUR 5 ATmega48PA PU 32A 32A 32CC1 32CC1 28M1 28M1 32M1 A 32M1 A 28P3 Industrial 40 C to 85 C ATmega48PA AN ATmega48PA ANR 4 ATmega48PA MMN ATmega48PA MMNR 4 ATmega48PA MN ATmega48PA MNR 4 ATmega48PA PN 32A 32A 28M1 28M1 32M1 A 32M1 A 28P3 Industrial 40 C to 105 C Package Type 32A 32 lead Thin 1 0mm Plastic Quad Flat Pac...

Page 542: ...2 Package 1 Operational Range 20 3 1 8 5 5 ATmega88A AU ATmega88A AUR 5 ATmega88A CCU ATmega88A CCUR 5 ATmega88A MMH 4 ATmega88A MMHR 4 5 ATmega88A MU ATmega88A MUR 5 ATmega88A PU 32A 32A 32CC1 32CC1 28M1 28M1 32M1 A 32M1 A 28P3 Industrial 40 C to 85 C Package Type 32A 32 lead Thin 1 0mm Plastic Quad Flat Package TQFP 32CC1 32 ball 4 x 4 x 0 6mm package ball pitch 0 5mm Ultra Thin Fine Pitch Ball ...

Page 543: ...mega88PA CCUR 5 ATmega88PA MMH 4 ATmega88PA MMHR 4 5 ATmega88PA MU ATmega88PA MUR 5 ATmega88PA PU 32A 32A 32CC1 32CC1 28M1 28M1 32M1 A 32M1 A 28P3 Industrial 40 C to 85 C ATmega88PA AN ATmega88PA ANR 5 ATmega88PA MMN ATmega88PA MMNR 5 ATmega88PA MN ATmega88PA MNR 5 ATmega88PA PN 32A 32A 28M1 28M1 32M1 A 32M1 A 28P3 Industrial 40 C to 105 C Package Type 32A 32 lead Thin 1 0mm Plastic Quad Flat Pack...

Page 544: ...Package 1 Operational Range 20 1 8 5 5 ATmega168A AU ATmega168A AUR 5 ATmega168A CCU ATmega168A CCUR 5 ATmega168A MMH 4 ATmega168A MMHR 4 5 ATmega168A MU ATmega168A MUR 5 ATmega168A PU 32A 32A 32CC1 32CC1 28M1 28M1 32M1 A 32M1 A 28P3 Industrial 40 C to 85 C Package Type 32A 32 lead Thin 1 0mm Plastic Quad Flat Package TQFP 32CC1 32 ball 4 x 4 x 0 6 mm package ball pitch 0 5mm Ultra Thin Fine Pitch...

Page 545: ...ga168PA CCU ATmega168PA CCUR 5 ATmega168PA MMH 4 ATmega168PA MMHR 4 5 ATmega168PA MU ATmega168PA MUR 5 ATmega168PA PU 32A 32A 32CC1 32CC1 28M1 28M1 32M1 A 32M1 A 28P3 Industrial 40 C to 85 C 20 1 8 5 5 ATmega168PA AN ATmega168PA ANR 5 ATmega168PA MN ATmega168PA MNR 5 ATmega168PA PN 32A 32A 32M1 A 32M1 A 28P3 Industrial 40 C to 105 C Package Type 32A 32 lead Thin 1 0mm Plastic Quad Flat Package TQF...

Page 546: ...NiPdAu Lead Finish 5 Tape Reel Speed MHz Power Supply V Ordering Code 2 Package 1 Operational Range 20 3 1 8 5 5 ATmega328 AU ATmega328 AUR 5 ATmega328 MMH 4 ATmega328 MMHR 4 5 ATmega328 MU ATmega328 MUR 5 ATmega328 PU 32A 32A 28M1 28M1 32M1 A 32M1 A 28P3 Industrial 40 C to 85 C Package Type 32A 32 lead Thin 1 0mm Plastic Quad Flat Package TQFP 28M1 28 pad 4 x 4 x 1 0 body Lead Pitch 0 45mm Quad F...

Page 547: ...Code 2 Package 1 Operational Range 20 1 8 5 5 ATmega328P AU ATmega328P AUR 5 ATmega328P MMH 4 ATmega328P MMHR 4 5 ATmega328P MU ATmega328P MUR 5 ATmega328P PU 32A 32A 28M1 28M1 32M1 A 32M1 A 28P3 Industrial 40 C to 85 C ATmega328P AN ATmega328P ANR 5 ATmega328P MN ATmega328P MNR 5 ATmega328P PN 32A 32A 32M1 A 32M1 A 28P3 Industrial 40 C to 105 C Package Type 32A 32 lead Thin 1 0mm Plastic Quad Fla...

Page 548: ...e E1 E B Notes 1 This package conforms to JEDEC reference MS 026 Variation ABA 2 Dimensions D1 and E1 do not include mold protrusion Allowable protrusion is 0 25 mm per side Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch 3 Lead coplanarity is 0 10 mm maximum A 1 20 A1 0 05 0 15 A2 0 95 1 00 1 05 D 8 75 9 00 9 25 D1 6 90 7 00 7 10 Note 2 E 8 75 9 00 9 25 E1 6 ...

Page 549: ...0 25 0 30 0 35 1 b1 0 25 2 D 3 90 4 00 4 10 D1 2 50 BSC E 3 90 4 00 4 10 E1 2 50 BSC e 0 50 BSC 07 06 10 b1 COMMON DIMENSIONS Unit of Measure mm 1 2 3 4 5 6 B A C D E F E D e 32 Øb E D B A Pin 1 ID 0 08 A1 A D1 E1 A2 A1 BALL CORNER 1 2 3 4 5 6 F C SIDE VIEW BOTTOM VIEW TOP VIEW SYMBOL MIN NOM MAX NOTE Note1 Dimension b is measured at the maximum ball dia in a plane parallel to the seating plane No...

Page 550: ...tic Very Thin Quad Flat No Lead Package VQFN 10 24 08 SIDE VIEW Pin 1 ID BOTTOM VIEW TOP VIEW Note The terminal 1 ID is a Laser marked Feature D E e K A1 C A D2 E2 y L 1 2 3 b 1 2 3 0 45 COMMON DIMENSIONS Unit of Measure mm SYMBOL MIN NOM MAX NOTE A 0 80 0 90 1 00 A1 0 00 0 02 0 05 b 0 17 0 22 0 27 C 0 20 REF D 3 95 4 00 4 05 D2 2 35 2 40 2 45 E 3 95 4 00 4 05 E2 2 35 2 40 2 45 e 0 45 L 0 35 0 40 ...

Page 551: ...IMENSIONS Unit of Measure mm SYMBOL MIN NOM MAX NOTE D1 D E1 E e b A3 A2 A1 A D2 E2 0 08 C L 1 2 3 P P 0 1 2 3 A 0 80 0 90 1 00 A1 0 02 0 05 A2 0 65 1 00 A3 0 20 REF b 0 18 0 23 0 30 D D1 D2 2 95 3 10 3 25 4 90 5 00 5 10 4 70 4 75 4 80 4 70 4 75 4 80 4 90 5 00 5 10 E E1 E2 2 95 3 10 3 25 e 0 50 BSC L 0 30 0 40 0 50 P 0 60 12o Note JEDEC Standard MO 220 Fig 2 Anvil Singulation VHHD 2 TOP VIEW SIDE ...

Page 552: ...1 A1 B REF E B1 C L SEATING PLANE A 0º 15º D e eB B2 4 PLACES COMMON DIMENSIONS Unit of Measure mm SYMBOL MIN NOM MAX NOTE A 4 5724 A1 0 508 D 34 544 34 798 Note 1 E 7 620 8 255 E1 7 112 7 493 Note 1 B 0 381 0 533 B1 1 143 1 397 B2 0 762 1 143 L 3 175 3 429 C 0 203 0 356 eB 10 160 e 2 540 TYP Note 1 Dimensions D and E1 do not include mold Flash or Protrusion Mold Flash or Protrusion shall not exce...

Page 553: ...PA device 35 2 1 Rev D Analog MUX can be turned off when setting ACME bit 1 Analog MUX can be turned off when setting ACME bit If the ACME Analog Comparator Multiplexer Enabled bit in ADCSRB is set while MUX3 in ADMUX is 1 ADMUX 3 0 1xxx all MUX es are turned off until the ACME bit is cleared Problem Fix Workaround Clear the MUX3 bit before setting the ACME bit 35 3 Errata ATmega88A The revision l...

Page 554: ...ice 35 5 1 Rev E Analog MUX can be turned off when setting ACME bit 1 Analog MUX can be turned off when setting ACME bit If the ACME Analog Comparator Multiplexer Enabled bit in ADCSRB is set while MUX3 in ADMUX is 1 ADMUX 3 0 1xxx all MUX es are turned off until the ACME bit is cleared Problem Fix Workaround Clear the MUX3 bit before setting the ACME bit 35 6 Errata ATmega168PA The revision lette...

Page 555: ...exer Enabled bit in ADCSRB is set while MUX3 in ADMUX is 1 ADMUX 3 0 1xxx all MUX es are turned off until the ACME bit is cleared Problem Fix Workaround Clear the MUX3 bit before setting the ACME bit 2 Unstable 32kHz Oscillator The 32kHz oscillator does not work as system clock The 32kHz oscillator used as asyn chronous timer is inaccurate Problem Fix Workaround None 35 7 4 Rev A Analog MUX can be...

Page 556: ...ev B Analog MUX can be turned off when setting ACME bit Unstable 32kHz Oscillator 1 Analog MUX can be turned off when setting ACME bit If the ACME Analog Comparator Multiplexer Enabled bit in ADCSRB is set while MUX3 in ADMUX is 1 ADMUX 3 0 1xxx all MUX es are turned off until the ACME bit is cleared Problem Fix Workaround Clear the MUX3 bit before setting the ACME bit 2 Unstable 32kHz Oscillator ...

Page 557: ...rata ATmega328P on page 556 98 Updated the datasheet according to the Atmel new brand style guide 1 Added 32UFBGA Pinout Table 1 1 on page 2 2 Updated the SRAM Data Memory Figure 8 3 on page 19 3 Updated Ordering Information on page 540 with CCU and CCUR code related to 32CC1 Package drawing 4 32CC1 Package drawing added on Packaging Information on page 548 1 Updated Table 9 8 with correct value f...

Page 558: ...328 Updated Feature Description Updated Table 2 1 on page 6 Added note for BOD Disable on page 41 Added note on BOD and BODSE in MCUCR MCU Control Register on page 94 and Register Description on page 295 Added limitation informatin for the application Boot Loader Support Read While Write Self Programming on page 280 Added limitiation information for Program And Data Memory Lock Bits on page 297 Ad...

Page 559: ...t 10 7 3Status Register 10 7 4General Purpose Register File 12 7 5Stack Pointer 13 7 6Instruction Execution Timing 14 7 7Reset and Interrupt Handling 15 8 AVR Memories 17 8 1Overview 17 8 2In System Reprogrammable Flash Program Memory 17 8 3SRAM Data Memory 19 8 4EEPROM Data Memory 20 8 5I O Memory 21 8 6Register Description 22 9 System Clock and Clock Options 27 9 1Clock Systems and their Distrib...

Page 560: ...de 42 10 8Extended Standby Mode 43 10 9Power Reduction Register 43 10 10Minimizing Power Consumption 43 10 11Register Description 45 11 System Control and Reset 48 11 1Resetting the AVR 48 11 2Reset Sources 48 11 3Power on Reset 49 11 4External Reset 50 11 5Brown out Detection 50 11 6Watchdog System Reset 51 11 7Internal Voltage Reference 51 11 8Watchdog Timer 52 11 9Register Description 56 12 Int...

Page 561: ...e Match Output Unit 100 15 7Modes of Operation 101 15 8Timer Counter Timing Diagrams 106 15 9Register Description 108 16 16 bit Timer Counter1 with PWM 115 16 1Features 115 16 2Overview 115 16 3Accessing 16 bit Registers 117 16 4Timer Counter Clock Sources 120 16 5Counter Unit 121 16 6Input Capture Unit 122 16 7Output Compare Units 124 16 8Compare Match Output Unit 126 16 9Modes of Operation 127 1...

Page 562: ...ption 160 19 SPI Serial Peripheral Interface 168 19 1Features 168 19 2Overview 168 19 3SS Pin Functionality 173 19 4Data Modes 173 19 5Register Description 175 20 USART0 178 20 1Features 178 20 2Overview 178 20 3Clock Generation 179 20 4Frame Formats 182 20 5USART Initialization 184 20 6Data Transmission The USART Transmitter 185 20 7Data Reception The USART Receiver 188 20 8Asynchronous Data Rece...

Page 563: ...tems and Arbitration 242 22 9Register Description 243 23 Analog Comparator 248 23 1Overview 248 23 2Analog Comparator Multiplexed Input 248 23 3Register Description 249 24 Analog to Digital Converter 252 24 1Features 252 24 2Overview 252 24 3Starting a Conversion 254 24 4Prescaling and Conversion Timing 255 24 5Changing Channel or Reference Selection 257 24 6ADC Noise Canceler 258 24 7ADC Conversi...

Page 564: ... Programming the Flash 285 27 9Register Description 295 28 Memory Programming 297 28 1Program And Data Memory Lock Bits 297 28 2Fuse Bits 298 28 3Signature Bytes 301 28 4Calibration Byte 302 28 5Page Size 302 28 6Parallel Programming Parameters Pin Mapping and Commands 303 28 7Parallel Programming 305 28 8Serial Downloading 312 29 Electrical Characteristics 317 29 1Absolute Maximum Ratings 317 29 ...

Page 565: ...ummary 533 32 Instruction Set Summary 537 33 Ordering Information 540 33 1ATmega48A 540 33 2ATmega48PA 541 33 3ATmega88A 542 33 4ATmega88PA 543 33 5ATmega168A 544 33 6ATmega168PA 545 33 7ATmega328 546 33 8ATmega328P 547 34 Packaging Information 548 34 132A 548 34 232CC1 549 34 328M1 550 34 432M1 A 551 34 528P3 552 35 Errata 553 35 1Errata ATmega48A 553 35 2Errata ATmega48PA 553 35 3Errata ATmega88...

Page 566: ...viii 8271D AVR 05 11 ATmega48A PA 88A PA 168A PA 328 P 36 1Rev 8271D 05 11 557 36 2Rev 8271C 08 10 557 36 3Rev 8271B 04 10 557 36 4Rev 8271A 12 09 558 Table of Contents i ...

Page 567: ...FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTY OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRINGEMENT IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT INDIRECT CONSEQUENTIAL PUNITIVE ...

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