ATasicICE POD User Guide
ATasicICE POD User Guide
5
Note:
Pin numbering = {MSB,..., LSB}
1.5
ASIC POD
Resources
Figure 1-5.
Pod, On-Board Resources
1.5.1
SRAM (128K bytes)
The ASIC POD includes a 128K bytes SRAM which can be used as external memory to
the AVR core or as general purpose memory. The memory used is a standard asyn-
chronous SRAM with a maximum 20 ns access/cycle time. The pin-out to the FPGA for
the memory interface is shown below.
Note:
Pin numbering = {MSB,..., LSB}
PORTF 7:0
(GIO 47:40)
= {108, 109, 110, 111, 112, 113, 114, 115}
PORTG 7:0
(GIO 55:48)
= {97, 99, 100, 102, 103, 104, 105, 107}
PORTH 7:0
(GIO 63:56)
= {86, 87, 88, 92, 93, 94, 95, 96}
Ports (Continued)
Signal Name
FPGA pin-out (physical pin number)
POWER
SRAM
RS232 PORTS
EXTERNAL
OSCILLATOR
GENERAL I/O
Signal Name
FPGA pin-out (physical pin number)
(F)ADR 16:0
= {2, 239, 238, 233, 232, 221, 220, 214, 213, 210, 209, 203, 202, 188, 187,
184, 183}
(F)DAT 7:0
= {123, 129, 141, 148, 152, 159, 173, 177}
(GSRAM)CS\
= {191}
(GSRAM)OE\
= {190}
(GSRAM)WE\
= {189}
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