ATasicICE POD User Guide
1
ATasicICE POD
User Guide
1.0
Introduction
The AVR ATasicICE POD is an extension to the AVR ATasicICE (ASIC ICE) which
gives a quick start ASIC development platform for the AVR ASIC users. The ASIC POD
includes two example designs to demonstrate the interface between the AVR core and
the custom logic.
1.1
Description of
the ASIC ICE Pod
The ASIC ICE POD is based on a field programmable gate array (FPGA) that can be
programmed to function as a custom I/O logic for the AVR core. A set of 64 I/O pins from
the FPGA are made available to the user through connectors. In addition, the ASIC ICE
POD includes SRAM, RS232 ports, and a clock oscillator as on-board resources.
Figure 1-1.
ASIC ICE POD Block Diagram
This document describes how to configure the FPGA and to use the on-board resources
to the ASIC ICE POD. The ASIC ICE interface is described in the ICEPRO ASIC
Designer’s Guide together with the example designs.
1.2
Power Supply
It is recommended to use the emulator power supply which is available on the pod con-
nector. This is done by adding a jumper to the JP2 pins (default setting, see Figure 1-2).
Total current drawn from the emulator must not exceed 1A (@ 5V). At higher currents
AVR ATASICICE
ADR
AVR V2 CORE
PROGRAM
MEMORY
INTERNAL
DATA
MEMORY
HOST
INTERFACE
POD INTERFACE
CLOCK
GENERATION
LOGIC
DBUS
HOST PC
W/ AVR
STUDIO
POD
CTRL
www.BDTIC.com/ATMEL
