ATasicICE POD User Guide
4
ATasicICE POD User Guide
Note:
Pin numbering = {MSB,..., LSB}
1.4
General I/O Ports
The general I/O port connectors are labeled PORTA-PORTH on the pod card. These
ports are directly connected to the FPGA. Each port has eight I/O pins and two ground
pins. Short cables should be used when connecting additional logic on the port pins.
Figure 1-4.
Port Connector Pin-Out
WARNING! The general I/O ports are sensitive to electrostatic discharges.
Extended Signals (Reserved For Future Use)
Signal Name
FPGA pin-out (physical pin number)
IOEXTEND 4:0
= {43, 42, 41, 39, 38}
Clocks
Signal Name
FPGA pin-out (physical pin number)
CLKALWAYS
= {57}
EXTCLKIN
= {not connected to the FPGA}
EXTCLKEN
= {not connected to the FPGA}
CLKRUN
= {31}
CLKOSC
= {63}
CLKIO
= {118}
CLKSTOPIO
= {32}
CLKSTOPCORE
= {33}
CLKEN
= {44}
IOBUSY
= {28}
Ports
Signal Name
FPGA pin-out (physical pin number)
PORTA 7:0
(GIO 7:0)
= {167, 168, 169, 170, 171, 172, 175, 176}
PORTB 7:0
(GIO 15:8)
= {155, 156, 157, 160, 162, 163, 164, 165}
PORTC 7:0
(GIO 23:16)
= {142, 144, 145, 146, 147, 149, 153, 154}
PORTD 7:0
(GIO 31:24)
= {131, 132, 133, 134, 136, 137, 138, 139}
PORTE 7:0
(GIO 39:32)
= {116, 117, 124, 125, 126, 127, 128, 130}
0
6
7
G N D
1
2
3
4
5
G N D
P O R T x
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