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8126F–AVR–05/12

ATtiny13A

• Bits 1:0 – WGM0[1:0]: Waveform Generation Mode

Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-
form generation to be used, see

Table 11-8 on page 73

. Modes of operation supported by the

Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode,
and two types of Pulse Width Modulation (PWM) modes (see

“Modes of Operation” on page 64

Notes:

1. MAX = 0xFF
2. BOTTOM = 0x00

11.9.2

TCCR0B – Timer/Counter Control Register B

• Bit 7 – FOC0A: Force Output Compare A

The FOC0A bit is only active when the WGM bits specify a non-PWM mode.

However, for ensuring compatibility with future devices, this bit must be set to zero when
TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0A bit,
an immediate Compare Match is forced on the Waveform Generation unit. The OC0A output is
changed according to its COM0A[1:0] bits setting. Note that the FOC0A bit is implemented as a
strobe. Therefore it is the value present in the COM0A[1:0] bits that determines the effect of the
forced compare.

A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR0A as TOP.

The FOC0A bit is always read as zero.

Table 11-8.

Waveform Generation Mode Bit Description

Mode

WGM02

WGM01

WGM00

Timer/Counter
Mode of Operation

TOP

Update of

OCRx at

TOV Flag

Set on

0

0

0

0

Normal

0xFF

Immediate

MAX

1

0

0

1

PWM
(Phase Correct)

0xFF

TOP

BOTTOM

2

0

1

0

CTC

OCRA

Immediate

MAX

3

0

1

1

Fast PWM

0xFF

TOP

MAX

4

1

0

0

Reserved

–

–

–

5

1

0

1

PWM
(Phase Correct)

OCRA

TOP

BOTTOM

6

1

1

0

Reserved

–

–

–

7

1

1

1

Fast PWM

OCRA

TOP

TOP

Bit

7

6

5

4

3

2

1

0

FOC0A

FOC0B

–

–

WGM02

CS02

CS01

CS00

TCCR0B

Read/Write

W

W

R

R

R/W

R/W

R/W

R/W

Initial Value

0

0

0

0

0

0

0

0

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Summary of Contents for ATtiny13A

Page 1: ...oltage Reference Programmable Watchdog Timer with Separate On chip Oscillator On chip Analog Comparator Special Microcontroller Features debugWIRE On chip Debug System In System Programmable via SPI Port External and Internal Interrupt Sources Low Power Idle ADC Noise Reduction and Power down Modes Enhanced Power on Reset Circuit Programmable Brown out Detection Circuit with Software Disable Funct...

Page 2: ...10 PCINT5 RESET ADC0 dW PB5 PCINT3 CLKI ADC3 PB3 DNC DNC PCINT4 ADC2 PB4 DNC DNC GND DNC DNC VCC PB2 SCK ADC1 T0 PCINT2 DNC PB1 MISO AIN1 OC0B INT0 PCINT1 PB0 MOSI AIN0 OC0A PCINT0 DNC DNC DNC DNC DNC NOTE Bottom pad should be soldered to ground DNC Do Not Connect 1 2 3 4 5 10 QFN MLF 10 9 8 7 6 PCINT5 RESET ADC0 dW PB5 PCINT3 CLKI ADC3 PB3 DNC PCINT4 ADC2 PB4 GND VCC PB2 SCK ADC1 T0 PCINT2 DNC PB...

Page 3: ...he pull up resistors are activated The Port B pins are tri stated when a reset condition becomes active even if the clock is not running Port B also serves the functions of various special features of the ATtiny13A as listed on page 55 1 1 4 RESET Reset input A low level on this pin for longer than the minimum pulse length will generate a reset even if the clock is not running and provided the res...

Page 4: ...rsus processing speed 2 1 Block Diagram Figure 2 1 Block Diagram PROGRAM COUNTER INTERNAL OSCILLATOR WATCHDOG TIMER STACK POINTER PROGRAM FLASH SRAM MCU CONTROL REGISTER GENERAL PURPOSE REGISTERS INSTRUCTION REGISTER TIMER COUNTER0 INSTRUCTION DECODER DATA DIR REG PORT B DATA REGISTER PORT B PROGRAMMING LOGIC TIMING AND CONTROL MCU STATUS REGISTER STATUS REGISTER ALU PORT B DRIVERS PB 0 5 VCC GND ...

Page 5: ...hdog Timer with internal Oscillator and three soft ware selectable power saving modes The Idle mode stops the CPU while allowing the SRAM Timer Counter ADC Analog Comparator and Interrupt system to continue functioning The Power down mode saves the register contents disabling all chip functions until the next Inter rupt or Hardware Reset The ADC Noise Reduction mode stops the CPU and all I O modul...

Page 6: ...se various parts of the device These code examples assume that the part specific header file is included before compilation Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent Please confirm with the C compiler documen tation for more details 3 3 Data Retention Reliability Qualification results show that the project...

Page 7: ...emories and buses for program and data Instructions in the Program memory are executed with a single level pipelining While one instruction is being executed the next instruc tion is pre fetched from the Program memory This concept enables instructions to be executed in every clock cycle The Program memory is In System Reprogrammable Flash memory Flash Program Memory Instruction Register Instructi...

Page 8: ... the five different addressing modes supported in the AVR architecture The memory spaces in the AVR architecture are all linear and regular memory maps A flexible interrupt module has its control registers in the I O space with an additional Global Interrupt Enable bit in the Status Register All interrupts have a separate Interrupt Vector in the Interrupt Vector table The interrupts have priority ...

Page 9: ...the BLD instruction Bit 5 H Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations Half Carry is useful in BCD arithmetic See the Instruction Set Description for detailed information Bit 4 S Sign Bit S N V The S bit is always an exclusive or between the Negative Flag N and the Two s Complement Overflow Flag V See the Instruction Set Description for detailed info...

Page 10: ...in Figure 4 2 on page 10 each register is also assigned a Data memory address mapping them directly into the first 32 locations of the user Data Space Although not being physically implemented as SRAM locations this memory organization provides great flexibility in access of the registers as the X Y and Z pointer registers can be set to index any register in the file 4 4 1 The X register Y registe...

Page 11: ...inter must be set to point above 0x60 The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction and it is incremented by two when data is popped ...

Page 12: ...is executed and the result is stored back to the destination register Figure 4 5 Single Cycle ALU Operation 4 7 Reset and Interrupt Handling The AVR provides several different interrupt sources These interrupts and the separate Reset Vector each have a separate Program Vector in the Program memory space All interrupts are assigned individual enable bits which must be written logic one together wit...

Page 13: ... and remembered until the Global Interrupt Enable bit is set and will then be executed by order of priority The second type of interrupts will trigger as long as the interrupt condition is present These interrupts do not necessarily have Interrupt Flags If the interrupt condition disappears before the interrupt is enabled the interrupt will not be triggered When the AVR exits from an interrupt it ...

Page 14: ...s during execution of a multi cycle instruction this instruction is completed before the interrupt is served If an interrupt occurs when the MCU is in sleep mode the interrupt execution response time is increased by four clock cycles This increase comes in addition to the start up time from the selected sleep mode A return from an interrupt handling routine takes four clock cycles During these fou...

Page 15: ...llocated within the entire Program memory address space see the LPM Load Program memory instruction description Timing diagrams for instruction fetch and execution are presented in Instruction Execution Tim ing on page 12 Figure 5 1 Program Memory Map 5 2 SRAM Data Memory Figure 5 2 on page 16 shows how the ATtiny13A SRAM Memory is organized The lower 160 Data memory locations address both the Reg...

Page 16: ...rformed in two clkCPU cycles as described in Figure 5 3 Figure 5 3 On chip Data SRAM Access Cycles 5 3 EEPROM Data Memory The ATtiny13A contains 64 bytes of data EEPROM memory It is organized as a separate data space in which single bytes can be read and written The EEPROM has an endurance of at least 100 000 write erase cycles The access between the EEPROM and the CPU is described in the followin...

Page 17: ...ramming time is given in Table 5 1 on page 21 The EEPE bit remains set until the erase and write operations are completed While the device is busy with programming it is not possi ble to do any other EEPROM operations 5 3 3 Split Byte Programming It is possible to split the erase and write cycle in two different operations This may be useful if the system requires short access time for some limite...

Page 18: ...Examples on page 6 Assembly Code Example EEPROM_write Wait for completion of previous write sbic EECR EEPE rjmp EEPROM_write Set Programming mode ldi r16 0 EEPM1 0 EEPM0 out EECR r16 Set up address r17 in address register out EEARL r17 Write data r16 to data register out EEDR r16 Write logical one to EEMPE sbi EECR EEMPE Start eeprom write by setting EEPE sbi EECR EEPE ret C Code Example void EEPR...

Page 19: ...ow EEPROM data corruption can easily be avoided by following this design recommendation Keep the AVR RESET active low during periods of insufficient power supply voltage This can be done by enabling the internal Brown out Detector BOD If the detection level of the internal BOD does not match the needed detection level an external low VCC reset protection circuit can be used If a reset occurs while...

Page 20: ...ll only operate on the specified bit and can therefore be used on registers containing such Status Flags The CBI and SBI instructions work with reg isters 0x00 to 0x1F only The I O and Peripherals Control Registers are explained in later sections 5 5 Register Description 5 5 1 EEARL EEPROM Address Register Bits 7 6 Res Reserved Bits These bits are reserved bits in the ATtiny13A and will always rea...

Page 21: ...Ready Interrupt generates a constant inter rupt when Non volatile memory is ready for programming Bit 2 EEMPE EEPROM Master Program Enable The EEMPE bit determines whether writing EEPE to one will have effect or not When EEMPE is set setting EEPE within four clock cycles will program the EEPROM at the selected address If EEMPE is zero setting EEPE will have no effect When EEMPE has been written to...

Page 22: ...tten to one to trigger the EEPROM read The EEPROM read access takes one instruction and the requested data is available immediately When the EEPROM is read the CPU is halted for four cycles before the next instruction is executed The user should poll the EEPE bit before starting the read opera tion If a write operation is in progress it is neither possible to read the EEPROM nor to change the EEAR...

Page 23: ...e the Status Register and the Data memory holding the Stack Pointer Halting the CPU clock inhibits the core from performing general operations and calculations 6 1 2 I O Clock clkI O The I O clock is used by the majority of the I O modules like Timer Counter The I O clock is also used by the External Interrupt module but note that some external interrupts are detected by asynchronous logic allowin...

Page 24: ...scillator operation before instruction execution starts When the CPU starts from reset there is an additional delay allowing the power to reach a stable level before com mencing normal operation The Watchdog Oscillator is used for timing this real time part of the start up time The number of WDT Oscillator cycles used for each time out is shown in Table 6 2 6 2 1 External Clock To drive the device...

Page 25: ...e 6 4 If selected it will operate with no external components Note 1 The device is shipped with this option selected During reset hardware loads the calibration data into the OSCCAL register and thereby auto matically calibrates the oscillator There are separate calibration bytes for 4 8 and 9 6 MHz operation but only one is automatically loaded during reset see section Calibration Bytes on page 1...

Page 26: ...ith longest start up time and an initial system clock prescaling of 8 This default setting ensures that all users can make their desired clock source setting using an In System or High voltage Programmer 6 3 System Clock Prescaler The ATtiny13A system clock can be divided by setting the CLKPR Clock Prescale Register on page 28 This feature can be used to decrease power consumption when the require...

Page 27: ...l Oscillator to remove process vari ations from the Oscillator frequency This is done automatically during Chip Reset When OSCCAL is zero the lowest available frequency is chosen Writing non zero values to this regis ter will increase the frequency of the internal Oscillator Writing 0x7F to the register gives the highest available frequency The calibrated Oscillator is used to time EEPROM and Flas...

Page 28: ...e followed to change the CLKPS bits 1 Write the Clock Prescaler Change Enable CLKPCE bit to one and all other bits in CLKPR to zero 2 Within four cycles write the desired value to CLKPS while writing a zero to CLKPCE Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted The CKDIV8 Fuse determines the initial value of the CLKPS bits If CKDIV...

Page 29: ...32 0 1 1 0 64 0 1 1 1 128 1 0 0 0 256 1 0 0 1 Reserved 1 0 1 0 Reserved 1 0 1 1 Reserved 1 1 0 0 Reserved 1 1 0 1 Reserved 1 1 1 0 Reserved 1 1 1 1 Reserved Table 6 8 Clock Prescaler Select Continued CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor ...

Page 30: ...errupt routine and resumes execution from the instruction following SLEEP The contents of the Register File and SRAM are unaltered when the device wakes up from sleep If a reset occurs during sleep mode the MCU wakes up and executes from the Reset Vector Note that if a level triggered interrupt is used for wake up from Power down mode the changed level must be held for some time to wake up the MCU...

Page 31: ...EVEL fuses see Table 17 3 on page 104 the BOD is actively monitoring the supply voltage during a sleep period It is possible to save power by disabling the BOD by software in Power Down sleep mode The sleep mode power consumption will then be at the same level as when BOD is globally disabled by fuses If BOD is disabled by software the BOD function is turned off immediately after entering the slee...

Page 32: ...ator should be dis abled in all sleep modes Otherwise the Internal Voltage Reference will be enabled independent of sleep mode Refer to Analog Comparator on page 79 for details on how to con figure the Analog Comparator 7 4 3 Brown out Detector If the Brown out Detector is not needed in the application this module should be turned off If the Brown out Detector is enabled by the BODLEVEL fuses it w...

Page 33: ...trol bits for disabling the BOD by software Bit 1 BODS BOD Sleep In order to disable BOD during sleep the BODS bit must be written to logic one This is controlled by a timed sequence and the enable bit BODSE First both BODS and BODSE must be set to one Second within four clock cycles BODS must be set to one and BODSE must be set to zero The BODS bit is active three clock cycles after it is set A s...

Page 34: ... zero Bit 1 PRTIM0 Power Reduction Timer Counter0 Writing a logic one to this bit shuts down the Timer Counter0 module When the Timer Counter0 is enabled operation will continue like before the shutdown Bit 0 PRADC Power Reduction ADC Writing a logic one to this bit shuts down the ADC The ADC must be disabled before shut down The analog comparator cannot be used when the ADC is shut down Table 7 2...

Page 35: ...eters of the reset circuitry Figure 8 1 Reset Logic The I O ports of the AVR are immediately reset to their initial state when a reset source goes active This does not require any clock source to be running After all reset sources have gone inactive a delay counter is invoked stretching the internal reset This allows the power to reach a stable level before normal operation starts The time out per...

Page 36: ...generated by an On chip detection circuit The detection level is defined in System and Reset Characteristics on page 120 The POR is activated whenever VCC is below the detection level The POR circuit can be used to trigger the Start up Reset as well as to detect a failure in supply voltage A Power on Reset POR circuit ensures that the device is reset from Power on Reaching the Power on Reset thres...

Page 37: ...ration by comparing it to a fixed trigger level The trigger level for the BOD can be selected by the BODLEVEL fuses The trigger level has a hysteresis to ensure spike free Brown out Detection The hysteresis on the detection level should be interpreted as VBOT VBOT VHYST 2 and VBOT VBOT VHYST 2 When the BOD is enabled and VCC decreases to a value below the trigger level VBOT in Figure 8 5 on page 3...

Page 38: ...not always turned on The reference is on during the following situations When the BOD is enabled by programming the BODLEVEL 1 0 fuse When the bandgap reference is connected to the Analog Comparator by setting the ACBG bit in ACSR When the ADC is enabled Thus when the BOD is not enabled after setting the ACBG bit or enabling the ADC the user must always allow the reference to start up before the o...

Page 39: ...e allow a safe shutdown by saving critical parameters before a system reset The Watchdog always on WDTON fuse if programmed will force the Watchdog Timer to Sys tem Reset mode With the fuse programmed the System Reset mode bit WDE and Interrupt mode bit WDTIE are locked to 1 and 0 respectively To further ensure program security altera tions to the Watchdog set up must follow timed sequences The se...

Page 40: ...dle the Watchdog this might lead to an eternal loop of time out resets To avoid this situa Assembly Code Example WDT_off Turn off global interrupt cli Reset Watchdog Timer wdr Clear WDRF in MCUSR in r16 MCUSR andi r16 0xff 1 WDRF out MCUSR r16 Write logical one to WDCE and WDE Keep old prescaler setting to prevent unintentional time out in r16 WDTCR ori r16 1 WDCE 1 WDE out WDTCR r16 Turn off WDT ...

Page 41: ...esult in a time out when switching to a shorter time out period Assembly Code Example WDT_Prescaler_Change Turn off global interrupt cli Reset Watchdog Timer wdr Start timed sequence in r16 WDTCR ori r16 1 WDCE 1 WDE out WDTCR r16 Got four cycles to set the new values from here Set new prescaler time out value 64K cycles 0 5 s ldi r16 1 WDE 1 WDP2 1 WDP0 out WDTCR r16 Finished setting new values u...

Page 42: ...eset Flags 8 5 2 WDTCR Watchdog Timer Control Register Bit 7 WDTIF Watchdog Timer Interrupt Flag This bit is set when a time out occurs in the Watchdog Timer and the Watchdog Timer is config ured for interrupt WDTIF is cleared by hardware when executing the corresponding interrupt handling vector Alternatively WDTIF is cleared by writing a logic one to the flag When the I bit in SREG and WDTIE are...

Page 43: ...F must be cleared first This feature ensures multiple resets during con ditions causing failure and a safe start up after the failure Bit 5 2 0 WDP 3 0 Watchdog Timer Prescaler 3 2 1 and 0 The WDP 3 0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is run ning The different prescaling values and their corresponding time out periods are shown in Table 8 2 on page 43 Table 8 1 W...

Page 44: ... AVR 05 12 ATtiny13A 1 0 1 0 Reserved 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Table 8 2 Watchdog Timer Prescale Select Continued WDP3 WDP2 WDP1 WDP0 Number of WDT Oscillator Cycles Typical Time out at VCC 5 0V ...

Page 45: ... 0x0004 rjmp EE_RDY EEPROM Ready Handler 0x0005 rjmp ANA_COMP Analog Comparator Handler 0x0006 rjmp TIM0_COMPA Timer0 CompareA Handler 0x0007 rjmp TIM0_COMPB Timer0 CompareB Handler 0x0008 rjmp WATCHDOG Watchdog Interrupt Handler 0x0009 rjmp ADC ADC Conversion Handler 0x000A RESET ldi r16 low RAMEND Main program start 0x000B out SPL r16 Set Stack Pointer to top of RAM 0x000C sei Enable interrupts ...

Page 46: ...stems and their Distribution on page 23 9 2 1 Low Level Interrupt A low level interrupt on INT0 is detected asynchronously This implies that this interrupt can be used for waking the part also from sleep modes other than Idle mode The I O clock is halted in all sleep modes except Idle mode Note that if a level triggered interrupt is used for wake up from Power down the required level must be held ...

Page 47: ...xter nal pin interrupt is enabled The Interrupt Sense Control0 bits 1 0 ISC01 and ISC00 in the MCU Control Register MCUCR define whether the external interrupt is activated on rising and or fall ing edge of the INT0 pin or level sensed Activity on the pin will cause an interrupt request even if INT0 is configured as an output The corresponding interrupt of External Interrupt Request 0 is executed ...

Page 48: ...e I bit in SREG and the PCIE bit in GIMSK are set one the MCU will jump to the cor responding Interrupt Vector The flag is cleared when the interrupt routine is executed Alternatively the flag can be cleared by writing a logical one to it 9 3 4 PCMSK Pin Change Mask Register Bits 7 6 Res Reserved Bits These bits are reserved bits in the ATtiny13A and will always read as zero Bits 5 0 PCINT 5 0 Pin...

Page 49: ...er case n represents the bit number However when using the register or bit defines in a program the precise form must be used For example PORTB3 for bit no 3 in Port B here documented generally as PORTxn The physical I O Regis ters and bit locations are listed in Register Description on page 57 Three I O memory address locations are allocated for each port one each for the Data Register PORTx Data...

Page 50: ...g the Pin Each port pin consists of three register bits DDxn PORTxn and PINxn As shown in Register Description on page 57 the DDxn bits are accessed at the DDRx I O address the PORTxn bits at the PORTx I O address and the PINxn bits at the PINx I O address The DDxn bit in the DDRx Register selects the direction of this pin If DDxn is written logic one Pxn is configured as an output pin If DDxn is ...

Page 51: ...ot notice the difference between a strong high driver and a pull up If this is not the case the PUD bit in the MCUCR Register can be set to disable all pull ups in all ports Switching between input with pull up and output low generates the same problem The user must use either the tri state DDxn PORTxn 0b00 or the output high state DDxn PORTxn 0b10 as an intermediate step Table 10 1 summarizes the...

Page 52: ...wo arrows tpd max and tpd min a single signal transition on the pin will be delayed between and 1 system clock period depending upon the time of assertion When reading back a software assigned pin value a nop instruction must be inserted as indi cated in Figure 10 4 on page 52 The out instruction sets the SYNC LATCH signal at the positive edge of the clock In this case the delay tpd through the sy...

Page 53: ...e schmitt trigger The signal denoted SLEEP in the figure is set by the MCU Sleep Controller in Power down mode Power save mode and Standby mode to avoid high power consumption if some input signals are left floating or have an analog signal level close to VCC 2 SLEEP is overridden for port pins enabled as external interrupt pins If the external interrupt request is not enabled SLEEP is active also...

Page 54: ...s if the pin is accidentally configured as an output 10 3 Alternate Port Functions Most port pins have alternate functions in addition to being general digital I Os Figure 10 5 shows how port pin control signals from the simplified Figure 10 2 on page 50 can be overridden by alternate functions Figure 10 5 Alternate Port Functions Note WRx WPx WDx RRx RPx and RDx are common to all pins within the ...

Page 55: ... If this signal is cleared the Output driver is enabled by the DDxn Register bit DDOV Data Direction Override Value If DDOE is set the Output Driver is enabled disabled when DDOV is set cleared regardless of the setting of the DDxn Register bit PVOE Port Value Override Enable If this signal is set and the Output Driver is enabled the port value is controlled by the PVOV signal If PVOE is cleared a...

Page 56: ...terrupt 0 Source 2 PB1 MISO SPI Master Data Input Slave Data Output AIN1 Analog Comparator Negative Input OC0B Timer Counter0 Compare Match B Output INT0 External Interrupt 0 Input PCINT1 Pin Change Interrupt 0 Source 1 PB0 MOSI SPI Master Data Output Slave Data Input AIN0 Analog Comparator Positive Input OC0A Timer Counter0 Compare Match A output PCINT0 Pin Change Interrupt 0 Source 0 Table 10 4 ...

Page 57: ... Name PB2 SCK ADC1 T0 PCINT2 PB1 MISO AIN1 OC0B INT0 PCINT1 PB0 MOSI AIN0 AREF OC0A PCINT0 PUOE 0 0 0 PUOV 0 0 0 DDOE 0 0 0 DDOV 0 0 0 PVOE 0 OC0B Enable OC0A Enable PVOV 0 OC0B OC0A PTOE 0 0 0 DIEOE PCINT2 PCIE ADC1D PCINT1 PCIE AIN1D PCINT0 PCIE AIN0D DIEOV ADC1D AIN1D AIN0D DI T0 PCINT2 Input INT0 PCINT1 Input PCINT0 Input AIO ADC1 Input Analog Comparator Negative Input Analog Comparator Positi...

Page 58: ...6F AVR 05 12 ATtiny13A 10 4 4 PINB Port B Input Pins Address Bit 7 6 5 4 3 2 1 0 0x16 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 PINB Read Write R R R W R W R W R W R W R W Initial Value 0 0 N A N A N A N A N A N A ...

Page 59: ...ram execution timing event man agement and wave generation A simplified block diagram of the 8 bit Timer Counter is shown in Figure 11 1 on page 59 For the actual placement of I O pins refer to Pinout of ATtiny13A on page 2 CPU accessible I O Registers including I O bits and I O pins are shown in bold The device specific I O Register and bit locations are listed in the Register Description on page...

Page 60: ...finitions Many register and bit references in this section are written in general form A lower case n replaces the Timer Counter number in this case 0 A lower case x replaces the Output Com pare Unit in this case Compare Unit A or Compare Unit B However when using the register or bit defines in a program the precise form must be used i e TCNT0 for accessing Timer Counter0 counter value and so on T...

Page 61: ...ut Compare output OC0A For more details about advanced counting sequences and waveform generation see Modes of Opera tion on page 64 The Timer Counter Overflow Flag TOV0 is set according to the mode of operation selected by the WGM0 1 0 bits TOV0 can be used for generating a CPU interrupt 11 5 Output Compare Unit The 8 bit comparator continuously compares TCNT0 with the Output Compare Registers OC...

Page 62: ... Compare FOC0x bit Forcing Compare Match will not set the OCF0x Flag or reload clear the timer but the OC0x pin will be updated as if a real Compare Match had occurred the COM0x 1 0 bits settings define whether the OC0x pin is set cleared or toggled 11 5 2 Compare Match Blocking by TCNT0 Write All CPU write operations to the TCNT0 Register will block any Compare Match that occur in the next timer ...

Page 63: ...ce Figure 11 4 on page 63 shows a simplified schematic of the logic affected by the COM0x 1 0 bit setting The I O Regis ters I O bits and I O pins in the figure are shown in bold Only the parts of the general I O Port Control Registers DDR and PORT that are affected by the COM0x 1 0 bits are shown When referring to the OC0x state the reference is for the internal OC0x Register not the OC0x pin If ...

Page 64: ...ed or toggled at a Compare Match See Compare Match Output Unit on page 63 For detailed timing information refer to Figure 11 8 on page 69 Figure 11 9 on page 69 Figure 11 10 on page 69 and Figure 11 11 on page 70 in Timer Counter Timing Diagrams on page 68 11 7 1 Normal Mode The simplest mode of operation is the Normal mode WGM0 2 0 0 In this mode the counting direction is always up incrementing a...

Page 65: ...sible on the port pin unless the data direction for the pin is set to output The waveform generated will have a maximum frequency of fOC0 fclk_I O 2 when OCR0A is set to zero 0x00 The waveform frequency is defined by the following equation The N variable represents the prescale factor 1 8 64 256 or 1024 As for the Normal mode of operation the TOV0 Flag is set in the same timer clock cycle that the...

Page 66: ... COM0x 1 0 bits to two will produce a non inverted PWM and an inverted PWM out put can be generated by setting the COM0x 1 0 to three Setting the COM0A 1 0 bits to one allows the AC0A pin to toggle on Compare Matches if the WGM02 bit is set This option is not available for the OC0B pin See Table 11 3 on page 71 The actual OC0x value will only be vis ible on the port pin if the data direction for t...

Page 67: ... Compare OC0x is cleared on the Compare Match between TCNT0 and OCR0x while upcounting and set on the Compare Match while down counting In inverting Output Compare mode the operation is inverted The dual slope operation has lower maximum operation frequency than single slope operation However due to the sym metric feature of the dual slope PWM modes these modes are preferred for motor control appl...

Page 68: ... a PWM waveform output in the phase correct PWM mode If the OCR0A is set equal to BOTTOM the output will be continuously low and if set equal to MAX the output will be continuously high for non inverted PWM mode For inverted PWM the output will have the opposite logic values At the very start of period 2 in Figure 11 7 on page 67 OCn has a transition from high to low even though there is no Compar...

Page 69: ..._I O 8 Figure 11 10 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC mode and PWM mode where OCR0A is TOP Figure 11 10 Timer Counter Timing Diagram Setting of OCF0x with Prescaler fclk_I O 8 clkTn clkI O 1 TOVn clkI O TCNTn MAX 1 MAX BOTTOM BOTTOM 1 TOVn TCNTn MAX 1 MAX BOTTOM BOTTOM 1 clkI O clkTn clkI O 8 OCFnx OCRnx TCNTn OCRnx Value OCRnx 1 OCRnx OCRnx 1 OCRnx 2 clkI O...

Page 70: ... note that the Data Direction Register DDR bit corresponding to the OC0A pin must be set in order to enable the output driver When OC0A is connected to the pin the function of the COM0A 1 0 bits depends on the WGM0 2 0 bit setting Table 11 2 shows the COM0A 1 0 bit functionality when the WGM0 2 0 bits are set to a normal or CTC mode non PWM OCFnx OCRnx TCNTn CTC TOP TOP 1 TOP BOTTOM BOTTOM 1 clkI ...

Page 71: ...o However note that the Data Direction Register DDR bit corresponding to the OC0B pin must be set in order to enable the output driver When OC0B is connected to the pin the function of the COM0B 1 0 bits depends on the WGM0 2 0 bit setting Table 11 5 on page 72 shows the COM0B 1 0 bit functionality when the WGM0 2 0 bits are set to a normal or CTC mode non PWM Table 11 3 Compare Output Mode Fast P...

Page 72: ...erved Bits These bits are reserved bits in the ATtiny13A and will always read as zero Table 11 5 Compare Output Mode non PWM Mode COM0B1 COM0B0 Description 0 0 Normal port operation OC0B disconnected 0 1 Toggle OC0B on Compare Match 1 0 Clear OC0B on Compare Match 1 1 Set OC0B on Compare Match Table 11 6 Compare Output Mode Fast PWM Mode 1 COM0B1 COM0B0 Description 0 0 Normal port operation OC0B d...

Page 73: ... PWM mode When writing a logical one to the FOC0A bit an immediate Compare Match is forced on the Waveform Generation unit The OC0A output is changed according to its COM0A 1 0 bits setting Note that the FOC0A bit is implemented as a strobe Therefore it is the value present in the COM0A 1 0 bits that determines the effect of the forced compare A FOC0A strobe will not generate any interrupt nor wil...

Page 74: ...Clock Select The three Clock Select bits select the clock source to be used by the Timer Counter If external pin modes are used for the Timer Counter0 transitions on the T0 pin will clock the counter even if the pin is configured as an output This feature allows software control of the counting 11 9 3 TCNT0 Timer Counter Register The Timer Counter Register gives direct access both for read and wri...

Page 75: ...ch in Timer Counter occurs i e when the OCF0B bit is set in the Timer Counter Interrupt Flag Register TIFR0 Bit 2 OCIE0A Timer Counter0 Output Compare Match A Interrupt Enable When the OCIE0A bit is written to one and the I bit in the Status Register is set the Timer Counter0 Compare Match A interrupt is enabled The corresponding interrupt is executed if a Compare Match in Timer Counter0 occurs i ...

Page 76: ... in OCR0A Output Compare Register0 OCF0A is cleared by hardware when executing the cor responding interrupt handling vector Alternatively OCF0A is cleared by writing a logic one to the flag When the I bit in SREG OCIE0A Timer Counter0 Compare Match Interrupt Enable and OCF0A are set the Timer Counter0 Compare Match Interrupt is executed Bit 1 TOV0 Timer Counter0 Overflow Flag The bit TOV0 is set w...

Page 77: ...n external clock source applied to the T0 pin can be used as Timer Counter clock clkT0 The T0 pin is sampled once every system clock cycle by the pin synchronization logic The synchro nized sampled signal is then passed through the edge detector Figure 12 1 on page 77 shows a functional equivalent block diagram of the T0 synchronization and edge detector logic The registers are clocked at the posi...

Page 78: ...unter Control Register Bit 7 TSM Timer Counter Synchronization Mode Writing the TSM bit to one activates the Timer Counter Synchronization mode In this mode the value that is written to the PSR10 bit is kept hence keeping the Prescaler Reset signal asserted This ensures that the Timer Counter is halted and can be configured without the risk of advanc ing during configuration When the TSM bit is wr...

Page 79: ...r Analog Compar ator pin placement 13 1 Analog Comparator Multiplexed Input It is possible to select any of the ADC 3 0 pins to replace the negative input to the Analog Com parator The ADC multiplexer is used to select this input and consequently the ADC must be switched off to utilize this feature If the Analog Comparator Multiplexer Enable bit ACME in ADCSRB is set and the ADC is switched off AD...

Page 80: ...put of the Analog Compar ator When the bandgap reference is used as input to the Analog Comparator it will take certain time for the voltage to stabilize If not stabilized the first value may give a wrong value Bit 5 ACO Analog Comparator Output The output of the Analog Comparator is synchronized and then directly connected to ACO The synchronization introduces a delay of 1 2 clock cycles Bit 4 AC...

Page 81: ...put Disable When this bit is written logic one the digital input buffer on the AIN1 0 pin is disabled The corre sponding PIN Register bit will always read as zero when this bit is set When an analog signal is applied to the AIN1 0 pin and the digital input from this pin is not needed this bit should be writ ten logic one to reduce power consumption in the digital input buffer Table 13 2 ACIS1 ACIS...

Page 82: ...errupt on ADC Conversion Complete Sleep Mode Noise Canceler 14 2 Overview The ATtiny13A features a 10 bit successive approximation ADC A block diagram of the ADC is shown in Figure 14 1 Figure 14 1 Analog to Digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ 8 BIT DATA BUS 15 0 ADC MULTIPLEXER SELECT ADMUX ADC CTRL STATUS REGISTER ADCSRA ADC DATA REGISTER ADCH ADCL ADIE ADATE ADSC ADEN ...

Page 83: ...DCL has been read and a conversion completes before ADCH is read neither register is updated and the result from the conversion is lost When ADCH is read ADC access to the ADCH and ADCL Registers is re enabled The ADC has its own interrupt which can be triggered when a conversion completes When ADC access to the data registers is prohibited between reading of ADCH and ADCL the interrupt will trigg...

Page 84: ... conversion is in progress The ADSC bit will be read as one during a conversion independently of how the conversion was started 14 5 Prescaling and Conversion Timing By default the successive approximation circuitry requires an input clock frequency between 50 kHz and 200 kHz to get maximum resolution If a lower resolution than 10 bits is needed the input clock frequency to the ADC can be higher t...

Page 85: ...tabilized the first value read after the first conversion may be wrong The actual sample and hold takes place 1 5 ADC clock cycles after the start of a normal conver sion and 14 5 ADC clock cycles after the start of an first conversion When a conversion is complete the result is written to the ADC Data Registers and ADIF is set In Single Conversion mode ADSC is cleared simultaneously The software ...

Page 86: ...gram Auto Triggered Conversion In Free Running mode a new conversion will be started immediately after the conversion com pletes while ADSC remains high Figure 14 7 ADC Timing Diagram Free Running Conversion 1 2 3 4 5 6 7 8 9 10 11 12 13 Sign and MSB of Result LSB of Result ADC Clock Trigger Source ADIF ADCH ADCL Cycle Number 1 2 One Conversion Next Conversion Conversion Complete Prescaler Reset A...

Page 87: ...ot tell if the next conversion is based on the old or the new settings ADMUX can be safely updated in the following ways When ADATE or ADEN is cleared During conversion minimum one ADC clock cycle after the trigger event After a conversion before the Interrupt Flag used as trigger source is cleared When updating ADMUX in one of these conditions the new settings will affect the next ADC conversion ...

Page 88: ...interrupt will wake up the CPU and execute the ADC Conversion Complete interrupt routine If another interrupt wakes up the CPU before the ADC conversion is complete the interrupt will be executed and an ADC Conversion Complete interrupt request will be generated when the ADC conversion completes The CPU will remain in active mode until a new sleep command is executed Note that the ADC will not be ...

Page 89: ...hich might affect the accuracy of analog measurements When conversion accuracy is critical the noise level can be reduced by applying the following techniques Keep analog signal paths as short as possible Make sure analog tracks run over the analog ground plane Keep analog tracks well away from high speed switching digital tracks If any port pin is used as a digital output it mustn t switch while ...

Page 90: ...4 9 Offset Error Gain Error After adjusting for offset the Gain Error is found as the deviation of the last transition 0x3FE to 0x3FF compared to the ideal transition at 1 5 LSB below maximum Ideal value 0 LSB Figure 14 10 Gain Error Output Code VREF Input Voltage Ideal ADC Actual ADC Offset Error Output Code VREF Input Voltage Ideal ADC Actual ADC Gain Error ...

Page 91: ...ny code Ideal value 0 LSB Figure 14 11 Integral Non linearity INL Differential Non linearity DNL The maximum deviation of the actual code width the interval between two adjacent transitions from the ideal code width 1 LSB Ideal value 0 LSB Figure 14 12 Differential Non linearity DNL Output Code VREF Input Voltage Ideal ADC Actual ADC INL Output Code 0x3FF 0x000 0 VREF Input Voltage DNL 1 LSB ...

Page 92: ...Description 14 12 1 ADMUX ADC Multiplexer Selection Register Bits 7 4 2 Res Reserved Bits These bits are reserved bits in the ATtiny13A and will always read as zero Bit 6 REFS0 Reference Selection Bit This bit selects the voltage reference for the ADC as shown in Table 14 2 If this bit is changed during a conversion the change will not go in effect until this conversion is complete ADIF in ADCSRA ...

Page 93: ... ADC ADSC will read as one as long as a conversion is in progress When the conversion is complete it returns to zero Writing zero to this bit has no effect Bit 5 ADATE ADC Auto Trigger Enable When this bit is written to one Auto Triggering of the ADC is enabled The ADC will start a con version on a positive edge of the selected trigger signal The trigger source is selected by setting the ADC Trigg...

Page 94: ... updated until ADCH is read Consequently if the result is left adjusted and no more than 8 bit precision is required it is sufficient to read ADCH Otherwise ADCL must be read first then ADCH Table 14 4 ADC Prescaler Selections ADPS2 ADPS1 ADPS0 Division Factor 0 0 0 2 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 Bit 15 14 13 12 11 10 9 8 0x05 ADC9 ADC8 ADCH 0x04 ADC7 ADC6 ADC5 ADC4...

Page 95: ...A is set this will start a conversion Switching to Free Running mode ADTS 2 0 0 will not cause a trigger event even if the ADC Interrupt Flag is set 14 12 5 DIDR0 Digital Input Disable Register 0 Bits 5 2 ADC3D ADC0D ADC 3 0 Digital Input Disable When a bit is written logic one the digital input buffer on the corresponding ADC pin is disabled The corresponding PIN register bit will always read as ...

Page 96: ...tem uses a One wire bi directional interface to control the program flow execute AVR instructions in the CPU and to program the different non volatile memories 15 3 Physical Interface When the debugWIRE Enable DWEN fuse is programmed and lock bits are unprogrammed the debugWIRE system within the target device is activated The RESET port pin is configured as a wire AND open drain bi directional I O...

Page 97: ...y located on the same pin as External Reset RESET An External Reset source is therefore not supported when the debugWIRE is enabled The debugWIRE system accurately emulates all I O functions when running at full speed i e when the program in the CPU is running When the CPU is stopped care must be taken while accessing some of the I O Registers via the debugger AVR Studio See the debugWIRE docu men...

Page 98: ...es an effective Read Modify Write feature which allows the user software to first read the page do the necessary changes and then write back the modified data If alter native 2 is used it is not possible to read the old data while loading since the page is already erased The temporary page buffer can be accessed in a random sequence It is essential that the page address used in both the Page Erase...

Page 99: ...unter can be treated as having two different sections One section consisting of the least significant bits is addressing the words within a page while the most significant bits are addressing the pages This is shown in Figure 16 1 Note that the Page Erase and Page Write operations are addressed independently Therefore it is of major importance that the software addresses the same page in both the ...

Page 100: ...reading the lock bits or if no LPM instruction is executed within three CPU cycles or if no SPM instruction is executed within four CPU cycles When RFLB and SELFPRGEN are cleared LPM functions normally To read the lock bits follow the below procedure 1 Load the Z pointer with 0x0001 2 Set RFLB and SELFPRGEN bits in SPMCSR 3 Issuing an LPM instruction within three clock cycles will return lock bits...

Page 101: ...owing these design recommendations one is sufficient 1 Keep the AVR RESET active low during periods of insufficient power supply voltage This can be done by enabling the internal Brown out Detector BOD if the operating voltage matches the detection level If not an external low VCC reset protection circuit can be used If a reset occurs while a write operation is in progress the write operation will...

Page 102: ...d within four clock cycles The CPU is halted during the entire Page Write operation Bit 1 PGERS Page Erase If this bit is written to one at the same time as SELFPRGEN the next SPM instruction within four clock cycles executes Page Erase The page address is taken from the high part of the Z pointer The data in R1 and R0 are ignored The PGERS bit will auto clear upon completion of a Page Erase or if...

Page 103: ...ts before lock bits See section Fuse Bytes on page 104 2 1 means unprogrammed 0 means programmed Table 17 1 Lock Bit Byte Lock Bit Byte Bit No Description Default Value 1 7 1 unprogrammed 6 1 unprogrammed 5 1 unprogrammed 4 1 unprogrammed 3 1 unprogrammed 2 1 unprogrammed LB2 1 Lock bit 1 unprogrammed LB1 0 Lock bit 1 unprogrammed Table 17 2 Lock Bit Protection Modes Memory Lock Bits 1 2 Protectio...

Page 104: ...age 26 for details 4 The default value of SUT 1 0 results in maximum start up time for the default clock source See Table 18 3 on page 119 for details 5 The default setting of CKSEL 1 0 results in internal RC Oscillator 9 6 MHz See Table 18 3 on page 119 for details Table 17 3 Fuse High Byte Fuse Bit Bit No Description Default Value 7 1 unprogrammed 6 1 unprogrammed 5 1 unprogrammed SELFPRGEN 1 4 ...

Page 105: ...ere is a separate calibration byte for the internal oscillator in 4 8 MHz mode of operation but this data is not loaded automatically The hardware always loads the 9 6 MHz calibration data during reset To use separate calibration data for the oscillator in 4 8 MHz mode the OSCCAL register must be updated by firmware The calibration data for 4 8 MHz operation is located in the high byte at address ...

Page 106: ...edicated for the internal SPI interface When programming the EEPROM an auto erase cycle is built into the self timed programming operation in the Serial mode ONLY and there is no need to first execute the Chip Erase instruction The Chip Erase operation turns the content of every memory location in both the Program and EEPROM arrays into 0xFF Depending on CKSEL fuses a valid clock must be present T...

Page 107: ... the data low byte must be loaded before data high byte is applied for a given address The Program memory Page is stored by loading the Write Program memory Page instruction with the 5 MSB of the address If polling RDY BSY is not used the user must wait at least tWD_FLASH before issuing the next page See Table 17 8 on page 108 Accessing the serial pro gramming interface before the Flash write oper...

Page 108: ...r low data i to Program memory page at word address b Data low byte must be loaded before Data high byte is applied within the same address Write Program Memory Page 0100 1100 0000 000a bbbb xxxx xxxx xxxx Write Program memory Page at address a b Read EEPROM Memory 1010 0000 000x xxxx xxbb bbbb oooo oooo Read data o from EEPROM memory at address b Write EEPROM Memory 1100 0000 000x xxxx xxbb bbbb ...

Page 109: ... 1010 1100 1010 H000 xxxx xxxx iiii iiii Set fuse low high byte Set bit to 0 to program 1 to unprogram See Fuse Bytes on page 104 for details Read Signature Byte 0011 0000 000x xxxx xxxx xxbb oooo oooo Read Signature Byte o at address b Read Calibration Byte 0011 1000 000x xxxx 0000 000b oooo oooo Read Calibration Byte See Calibration Bytes on page 105 Poll RDY BSY 1111 0000 0000 0000 xxxx xxxx xx...

Page 110: ... pin 6 Wait at least 300µs before giving any serial instructions on SDI SII 7 Exit Programming mode by power the device down or by bringing RESET pin to 0V If the rise time of the Vcc is unable to fulfill the requirements listed above the following alterna tive algorithm can be used 1 Set Prog_enable pins listed in Table 17 11 to 000 RESET pin to 0 and Vcc to 0V 2 Apply 4 5 5 5V between VCC and GN...

Page 111: ... 0_0010_1100_00 x_xxxx_xxxx_xx 0_dddd_dddd_00 0_0011_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1101_00 x_xxxx_xxxx_xx Repeat after Instr 1 5 until the entire page buffer is filled or until all data within the page is filled See Note 1 SDI SII SDO 0_0000_0000_00 0_0111_1100_00 x_xxxx_xxxx_xx Instr 5 Load Flash High Address and Program Page SDI SII SDO 0_0000_000a_00 0_0001_1100_00 x_xxxx_xxxx_xx...

Page 112: ... 0_0100_1100_00 x_xxxx_xxxx_xx 0_A987_6543_00 0_0010_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_0100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 x_xxxx_xxxx_xx Wait after Instr 4 until SDO goes high Write A 3 0 to program the Fuse bit Write Fuse High Bits SDI SII SDO 0_0100_0000_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_000F_EDCB_00 0_0010_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_0100_00 x_xxxx...

Page 113: ...r reading a new 256 word window in Flash or 256 byte EEPROM This consideration also applies to Signature bytes reading 17 8 1 Chip Erase The Chip Erase will erase the Flash and EEPROM 1 memories plus lock bits The lock bits are not reset until the Program memory has been completely erased The fuse bits are not changed A Chip Erase must be performed before the Flash and or EEPROM are re programmed ...

Page 114: ... after Instr 3 until SDO goes high for the Page Programming cycle to finish 4 Repeat 2 through 3 until the entire Flash is programmed or until all data has been programmed 5 End Page Programming by Loading Command No Operation When writing or reading serial data to the ATtiny13A data is clocked on the rising edge of the serial clock see Figure 17 4 on page 115 Figure 18 5 on page 123 and Table 18 ...

Page 115: ...r until all data has been programmed 5 End Page Programming by Loading Command No Operation 17 8 4 Reading the Flash The algorithm for reading the Flash memory is as follows refer to Table 17 13 on page 111 1 Load Command Read Flash 2 Read Flash Low and High Bytes The contents at the selected address are available at serial output SDO 17 8 5 Reading the EEPROM The algorithm for reading the EEPROM ...

Page 116: ...7 8 7 Reading the Signature Bytes and Calibration Byte The algorithms for reading the Signature bytes and Calibration byte are shown in Table 17 13 on page 111 17 8 8 Power off sequence Set SCI to 0 Set RESET to 1 Turn VCC power off ...

Page 117: ...le 18 1 DC Characteristics TA 40 C to 85 C Symbol Parameter Condition Min Typ 1 Max Units VIL Input Low Voltage Any Pin as I O VCC 1 8 2 4V 0 5 0 2VCC 2 V VCC 2 4 5 5V 0 5 0 3VCC 2 V Input Low Voltage RESET Pin as Reset 4 VCC 1 8 5 5 0 5 0 2VCC 2 V VIH Input High Voltage Any Pin as I O VCC 1 8 2 4V 0 7VCC 3 VCC 0 5 V VCC 2 4 5 5V 0 6VCC 3 VCC 0 5 V Input High Voltage RESET Pin as Reset 4 VCC 1 8 5...

Page 118: ...H may exceed the related specification Pins are not guaranteed to source current greater than the listed test condition 7 Values are with external clock using methods described in Minimizing Power Consumption on page 32 Power Reduction is enabled PRR 0xFF and there is no I O drive 8 BOD Disabled 18 3 Speed The maximum operating frequency of the device depends on supply voltage VCC As shown in Figu...

Page 119: ...fixed voltage 18 4 2 External Clock Drive Figure 18 2 External Clock Drive Waveform Table 18 2 Calibration Accuracy of Internal RC Oscillator Calibration Method Target Frequency VCC Temperature Accuracy at given Voltage Temperature 1 Factory Calibration 4 8 9 6 MHz 3V 25 C 10 User Calibration Fixed frequency within 4 5 MHz 8 10 MHz Fixed voltage within 1 8 5 5V Fixed temperature within 40 C to 85 ...

Page 120: ...ut and Internal Voltage Characteristics Symbol Parameter Condition Min Typ Max Units VRST RESET Pin Threshold Voltage 0 2 VCC 0 9VCC V tRST Minimum pulse width on RESET Pin 1 VCC 1 8V VCC 3V VCC 5V 2000 700 400 2500 2500 2500 ns VHYST Brown out Detector Hysteresis 2 50 mV tBOD Min Pulse Width on Brown out Reset 2 2 µs VBG Internal bandgap reference voltage VCC 5V TA 25 C 1 0 1 1 1 2 V tBG Internal...

Page 121: ...C Symbol Parameter Condition Min Typ Max Units Resolution 10 Bits Absolute accuracy Including INL DNL and Quantization Gain and Offset Errors VREF 4V VCC 4V ADC clock 200 kHz 3 LSB VREF 4V VCC 4V ADC clock 1 MHz 4 LSB VREF 4V VCC 4V ADC clock 200 kHz Noise Reduction Mode 2 5 LSB VREF 4V VCC 4V ADC clock 1 MHz Noise Reduction Mode 3 5 LSB Integral Non Linearity INL Accuracy after Offset and Gain Ca...

Page 122: ...Frequency VCC 1 8 5 5V 0 1 MHz tCLCL Oscillator Period 1000 ns 1 tCLCL Oscillator Frequency VCC 2 7 5 5V 0 9 6 MHz tCLCL Oscillator Period 104 ns 1 tCLCL Oscillator Frequency VCC 4 5 5 5V 0 20 MHz tCLCL Oscillator Period 50 ns tSHSL SCK Pulse Width High VCC 1 8 5 5V 2 tCLCL 1 ns tSLSH SCK Pulse Width Low 2 tCLCL 1 ns tOVSH MOSI Setup to SCK High tCLCL ns tSHOX MOSI Hold after SCK High 2 tCLCL ns M...

Page 123: ...CC 5 0V 10 Unless otherwise noted Symbol Parameter Min Typ Max Units tSHSL SCI PB3 Pulse Width High 110 ns tSLSH SCI PB3 Pulse Width Low 110 ns tIVSH SDI PB0 SII PB1 Valid to SCI PB3 High 50 ns tSHIX SDI PB0 SII PB1 Hold after SCI PB3 High 50 ns tSHOV SCI PB3 High to SDO PB2 Valid 16 ns tWLWH_PFB Wait after Instr 3 for Write Fuse Bits 2 5 ms SDI PB0 SII PB1 SDO PB2 SCI PB3 tIVSH tSHSL tSLSH tSHIX ...

Page 124: ...th Watchdog Timer enabled and Power Down mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer The current drawn from pins with a capacitive load may be estimated for one pin as follows where VCC operating voltage CL load capacitance and fSW average switching frequency of I O pin 19 1 Supply Current of I O Modules Using Table 19 1 the typical characteris...

Page 125: ...t vs Frequency 1 20 MHz ACTIVE SUPPLY CURRENT vs LOW FREQUENCY PRR 0xFF 5 5 V 5 0 V 4 5 V 4 0 V 3 3 V 2 7 V 1 8 V 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz I CC mA ACTIVE SUPPLY CURRENT vs FREQUENCY PRR 0xFF 5 5 V 5 0 V 4 5 V 4 0 V 3 3 V 2 7 V 1 8 V 0 2 4 6 8 10 12 0 2 4 6 8 10 12 14 16 18 20 Frequency MHz I CC mA ...

Page 126: ...ply Current vs VCC Internal RC Oscillator 4 8 MHz ACTIVE SUPPLY CURRENT vs VCC INTERNAL RC OSCILLATOR 9 6 MHz 85 C 25 C 40 C 0 1 2 3 4 5 6 7 8 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ACTIVE SUPPLY CURRENT vs VCC INTERNAL RC OSCILLATOR 4 8 MHz 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 3 3 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 127: ...rent vs VCC 32 kHz External Clock ACTIVE SUPPLY CURRENT vs VCC INTERNAL WD OSCILLATOR 128 KHz 85 C 25 C 40 C 0 0 02 0 04 0 06 0 08 0 1 0 12 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ACTIVE SUPPLY CURRENT vs VCC 32 KHz EXTERNAL CLOCK PRR 0xFF 85 C 25 C 40 C 0 0 005 0 01 0 015 0 02 0 025 0 03 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 128: ... Current vs Frequency 1 20 MHz IDLE SUPPLY CURRENT vs LOW FREQUENCY PRR 0xFF 5 5 V 5 0 V 4 5 V 4 0 V 3 3 V 2 7 V 1 8 V 0 0 02 0 04 0 06 0 08 0 1 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz I CC mA IDLE SUPPLY CURRENT vs FREQUENCY PRR 0xFF 5 5 V 5 0 V 4 5 V 4 0 V 3 3 V 2 7 V 0 0 5 1 1 5 2 0 2 4 6 8 10 12 14 16 18 20 Frequency MHz I CC mA 1 8 V ...

Page 129: ...nt vs VCC Internal RC Oscillator 4 8 MHz IDLE SUPPLY CURRENT vs VCC INTERNAL RC OSCILLATOR 9 6 MHz 85 C 25 C 40 C 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA IDLE SUPPLY CURRENT vs VCC INTERNAL RC OSCILLATOR 4 8 MHz 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 130: ...t vs VCC 32 kHz External Clock IDLE SUPPLY CURRENT vs VCC INTERNAL WD OSCILLATOR 128 KHz 85 C 25 C 40 C 0 0 005 0 01 0 015 0 02 0 025 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA IDLE SUPPLY CURRENT vs VCC 32 KHz EXTERNAL OSCILLATOR PRR 0xFF 85 C 25 C 40 C 0 0 001 0 002 0 003 0 004 0 005 0 006 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 131: ... 19 14 Power down Supply Current vs VCC Watchdog Timer Enabled POWER DOWN SUPPLY CURRENT vs VCC WATCHDOG TIMER DISABLED 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA POWER DOWN SUPPLY CURRENT vs VCC WATCHDOG TIMER ENABLED 85 C 25 C 40 C 0 1 2 3 4 5 6 7 8 9 10 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ...

Page 132: ...hrough the Reset Pull up RESET SUPPLY CURRENT vs VCC EXCLUDING CURRENT THROUGH THE RESET PULLUP 5 5 V 5 0 V 4 5 V 4 0 V 3 3 V 2 7 V 1 8 V 0 0 01 0 02 0 03 0 04 0 05 0 06 0 07 0 08 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz I CC mA RESET SUPPLY CURRENT vs VCC EXCLUDING CURRENT THROUGH THE RESET PULLUP 5 5 V 5 0 V 4 5 V 4 0 V 3 3 V 2 7 V 1 8 V 0 0 2 0 4 0 6 0 8 1 1 2 1 4 0 2 4 6 8 10 12 1...

Page 133: ...rownout Detector Current vs VCC Figure 19 18 ADC Current vs VCC BROWNOUT DETECTOR CURRENT vs VCC 85 C 25 C 40 C 0 5 10 15 20 25 30 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ADC CURRENT vs VCC f 1 0 MHz 40 C 25 C 85 C 0 50 100 150 200 250 300 350 400 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ...

Page 134: ...Programming Current vs VCC ANALOG COMPARATOR CURRENT vs VCC f 1 0 MHz 40 C 25 C 85 C 0 10 20 30 40 50 60 70 80 90 100 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA PROGRAMMING CURRENT vs VCC 85 C 25 C 40 C 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ...

Page 135: ...l up Resistor Current vs Input Voltage I O Pin VCC 3V 85 C 25 C 40 C I O PIN PULL UP RESISTOR CURRENT vs INPUT VOLTAGE VCC 1 8V 0 10 20 30 40 50 60 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 2 VOP V I OP uA 85 C 25 C 40 C I O PIN PULL UP RESISTOR CURRENT vs INPUT VOLTAGE VCC 3V 0 10 20 30 40 50 60 70 80 90 100 0 0 5 1 1 5 2 2 5 3 3 5 VOP V I OP uA ...

Page 136: ...tor Current vs Reset Pin Voltage VCC 1 8V I O PIN PULL UP RESISTOR CURRENT vs INPUT VOLTAGE VCC 5V 85 C 25 C 40 C 0 20 40 60 80 100 120 140 160 0 1 2 3 4 5 6 VOP V I OP uA 85 C 25 C 40 C RESET PULL UP RESISTOR CURRENT vs RESET PIN VOLTAGE VCC 1 8V 0 5 10 15 20 25 30 35 40 45 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 2 VRESET V I RESET uA ...

Page 137: ... up Resistor Current vs Reset Pin Voltage VCC 5V 85 C 25 C 40 C RESET PULL UP RESISTOR CURRENT vs RESET PIN VOLTAGE VCC 3V 0 10 20 30 40 50 60 70 80 0 0 5 1 1 5 2 2 5 3 3 5 VRESET V I RESET uA RESET PULL UP RESISTOR CURRENT vs RESET PIN VOLTAGE VCC 5V 85 C 25 C 40 C 0 20 40 60 80 100 120 140 0 1 2 3 4 5 6 VRESET V I RESET uA ...

Page 138: ...VOH I O Pin Output Voltage vs Source Current Low Power Pins VCC 3V I O PIN OUTPUT VOLTAGE vs SOURCE CURRENT LOW POWER PINS VCC 1 8V 85 C 25 C 40 C 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 2 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 IOH mA V OH V I O PIN OUTPUT VOLTAGE vs SOURCE CURRENT LOW POWER PINS VCC 3V 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 3 3 5 0 1 2 3 4 5 6 7 8 9 10 IOH mA V OH V ...

Page 139: ...put Voltage vs Sink Current Low Power Pins VCC 1 8V I O PIN OUTPUT VOLTAGE vs SOURCE CURRENT LOW POWER PINS VCC 5V 85 C 25 C 40 C 4 4 2 4 4 4 6 4 8 5 5 2 0 2 4 6 8 10 12 14 16 18 20 IOH mA V OH V I O PIN OUTPUT VOLTAGE vs SINK CURRENT LOW POWER PINS VCC 1 8V 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 3 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 IOL mA V OL V ...

Page 140: ...t Voltage vs Sink Current Low Power Pins VCC 5V I O PIN OUTPUT VOLTAGE vs SINK CURRENT LOW POWER PINS VCC 3V 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 2 3 4 5 6 7 8 9 10 IOL mA V OL V I O PIN OUTPUT VOLTAGE vs SINK CURRENT LOW POWER PINS VCC 5V 85 C 25 C 40 C 0 0 2 0 4 0 6 0 8 1 1 2 0 2 4 6 8 10 12 14 16 18 20 IOL mA V OL V ...

Page 141: ... 8V Figure 19 34 VOH I O Pin Output Voltage vs Source Current VCC 3V I O PIN OUTPUT VOLTAGE vs SOURCE CURRENT VCC 1 8V 85 C 25 C 40 C 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 2 0 1 2 3 4 5 6 IOH mA V OH V I O PIN OUTPUT VOLTAGE vs SOURCE CURRENT VCC 3V 85 C 25 C 40 C 1 5 1 7 1 9 2 1 2 3 2 5 2 7 2 9 3 1 0 1 2 3 4 5 6 7 8 9 10 IOH mA V OH V ...

Page 142: ...I O Pin Output Voltage vs Sink Current VCC 1 8V 85 C 25 C 40 C I O PIN OUTPUT VOLTAGE vs SOURCE CURRENT VCC 5V 4 4 2 4 4 4 6 4 8 5 5 2 0 2 4 6 8 10 12 14 16 18 20 IOH mA V OH V I O PIN OUTPUT VOLTAGE vs SINK CURRENT VCC 1 8V 85 C 25 C 40 C 0 0 05 0 1 0 15 0 2 0 25 0 3 0 35 0 4 0 45 0 5 0 1 2 3 4 5 6 IOL mA V OL V ...

Page 143: ...Pin Output Voltage vs Sink Current VCC 5V I O PIN OUTPUT VOLTAGE vs SINK CURRENT VCC 3V 85 C 25 C 40 C 0 0 05 0 1 0 15 0 2 0 25 0 3 0 35 0 4 0 45 0 1 2 3 4 5 6 7 8 9 10 IOL mA V OL V I O PIN OUTPUT VOLTAGE vs SINK CURRENT VCC 5V 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 2 4 6 8 10 12 14 16 18 20 IOL mA V OL V ...

Page 144: ...Voltage vs Source Current VCC 3V RESET AS I O PIN OUTPUT VOLTAGE vs SOURCE CURRENT VCC 1 8V 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 IOH mA V OH V 85 C 25 C 40 C 85 C 25 C 40 C RESET AS I O PIN OUTPUT VOLTAGE vs SOURCE CURRENT VCC 3V 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 IOH mA V OH V ...

Page 145: ...s I O Output Voltage vs Sink Current VCC 1 8V 85 C 25 C 40 C RESET AS I O PIN OUTPUT VOLTAGE vs SOURCE CURRENT VCC 5V 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 IOH mA V OH V 85 C 25 C 40 C RESET AS I O PIN OUTPUT VOLTAGE vs SINK CURRENT VCC 1 8V 0 0 2 0 4 0 6 0 8 1 0 0 1 0 2 0 3 0 4 0 5 0 6 IOL mA V OL V ...

Page 146: ... as I O Output Voltage vs Sink Current VCC 5V 85 C 25 C 40 C RESET AS I O PIN OUTPUT VOLTAGE vs SINK CURRENT VCC 3V 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 0 0 5 1 1 5 2 2 5 3 IOL mA V OL V 85 C 25 C 40 C RESET AS I O PIN OUTPUT VOLTAGE vs SINK CURRENT VCC 5V 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 IOL mA V OL V ...

Page 147: ...igure 19 46 VIL Input Threshold Voltage vs VCC I O Pin Read as 0 I O PIN INPUT THRESHOLD VOLTAGE vs VCC VIH I O PIN READ AS 1 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 3 3 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V I O PIN INPUT THRESHOLD VOLTAGE vs VCC VIL I O PIN READ AS 0 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V ...

Page 148: ...old Voltage vs VCC Reset Pin as I O Read as 1 I O PIN INPUT HYSTERESIS vs VCC 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Input Hysteresis V RESET PIN AS I O THRESHOLD VOLTAGE vs VCC VIH RESET READ AS 1 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 3 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V ...

Page 149: ...esis vs VCC Reset Pin as I O RESET PIN AS I O THRESHOLD VOLTAGE vs VCC VIL RESET READ AS 0 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V RESET PIN AS IO INPUT HYSTERESIS vs VCC VIL I O PIN READ AS 0 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Input Hysteresis V ...

Page 150: ... BOD Thresholds vs Temperature BODLEVEL is 2 7V BOD THRESHOLDS vs TEMPERATURE BODLEVEL 4 3V VCC RISING VCC FALLING 4 2 4 25 4 3 4 35 4 4 60 40 20 0 20 40 60 80 100 Temperature C Threshold V VCC RISING VCC FALLING BOD THRESHOLDS vs TEMPERATURE BODLEVEL 2 7V 2 6 2 65 2 7 2 75 2 8 60 40 20 0 20 40 60 80 100 Temperature C Threshold V ...

Page 151: ...Figure 19 54 Bandgap Voltage vs VCC VCC RISING VCC FALLING BOD THRESHOLDS vs TEMPERATURE BODLEVEL 1 8V 1 7 1 75 1 8 1 85 1 9 60 40 20 0 20 40 60 80 100 Temperature C Threshold V BANDGAP VOLTAGE vs VCC 85 C 25 C 40 C 1 06 1 08 1 1 1 12 1 14 1 5 2 2 5 3 3 5 4 4 5 5 5 5 Vcc V Bandgap Voltage V ...

Page 152: ... Input Threshold Voltage vs VCC Reset Pin Read as 0 RESET INPUT THRESHOLD VOLTAGE vs VCC VIH I O PIN READ AS 1 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V RESET INPUT THRESHOLD VOLTAGE vs VCC VIL I O PIN READ AS 0 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V ...

Page 153: ...gure 19 58 Minimum Reset Pulse Width vs VCC RESET PIN INPUT HYSTERESIS vs VCC 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Input Hysteresis V MINIMUM RESET PULSE WIDTH vs VCC 85 C 25 C 40 C 0 500 1000 1500 2000 0 1 2 3 4 5 6 VCC V Pulsewidth ns ...

Page 154: ...9 6 MHz RC Oscillator Frequency vs VCC CALIBRATED 9 6MHz RC OSCILLATOR FREQUENCY vs TEMPERATURE 5 5 V 4 5 V 2 7 V 1 8 V 9 9 1 9 2 9 3 9 4 9 5 9 6 9 7 9 8 9 9 10 40 20 0 20 40 60 80 100 Temperature C Frequency MHz CALIBRATED 9 6MHz RC OSCILLATOR FREQUENCY vs OPERATING VOLTAGE 85 C 25 C 40 C 9 9 2 9 4 9 6 9 8 10 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Frequency MHz ...

Page 155: ...cillator Frequency vs Temperature CALIBRATED 9 6MHz RC OSCILLATOR FREQUENCY vs OSCCAL VALUE VCC 3V 25 C 0 2 4 6 8 10 12 14 16 18 20 0 16 32 48 64 80 96 112 OSCCAL Frequency MHz CALIBRATED 4 8MHz RC OSCILLATOR FREQUENCY vs TEMPERATURE 5 5 V 4 0 V 2 7 V 1 8 V 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 60 40 20 0 20 40 60 80 100 Temperature Frequency MHz ...

Page 156: ... RC Oscillator Frequency vs Osccal Value CALIBRATED 4 8MHz RC OSCILLATOR FREQUENCY vs OPERATING VOLTAGE 85 C 25 C 40 C 4 2 4 4 4 6 4 8 5 5 2 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Frequency MHz CALIBRATED 4 8MHz RC OSCILLATOR FREQUENCY vs OSCCAL VALUE VCC 3V 25 C 0 1 2 3 4 5 6 7 8 9 10 0 16 32 48 64 80 96 112 OSCCAL Frequency MHz ...

Page 157: ...OSCILLATOR FREQUENCY vs OPERATING VOLTAGE 85 C 25 C 40 C 100000 102000 104000 106000 108000 110000 112000 114000 116000 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Frequency Hz WATCHDOG OSCILLATOR FREQUENCY vs TEMPERATURE 5 5 V 4 0 V 2 7 V 1 8 V 105000 106000 107000 108000 109000 110000 111000 112000 113000 114000 115000 60 40 20 0 20 40 60 80 100 Temperature Frequency kH ...

Page 158: ...6 CLKPR CLKPCE CLKPS3 CLKPS2 CLKPS1 CLKPS0 page 28 0x25 PRR PRTIM0 PRADC page 34 0x24 Reserved 0x23 Reserved 0x22 Reserved 0x21 WDTCR WDTIF WDTIE WDP3 WDCE WDE WDP2 WDP1 WDP0 page 42 0x20 Reserved 0x1F Reserved 0x1E EEARL EEPROM Address Register page 20 0x1D EEDR EEPROM Data Register page 20 0x1C EECR EEPM1 EEPM0 EERIE EEMPE EEPE EERE page 21 0x1B Reserved 0x1A Reserved 0x19 Reserved 0x18 PORTB PO...

Page 159: ...t accessible using the SBI and CBI instructions In these registers the value of single bits can be checked by using the SBIS and SBIC instructions ome of the Status Flags are cleared by writing a logical one to them Note that unlike most other AVRs the CBI and SBI instructions will only operation the specified bit and can therefore be used on registers containing such Status Flags The CBI and SBI ...

Page 160: ... Immediate Rd K Z N V C H 1 SBRC Rr b Skip if Bit in Register Cleared if Rr b 0 PC PC 2 or 3 None 1 2 3 SBRS Rr b Skip if Bit in Register is Set if Rr b 1 PC PC 2 or 3 None 1 2 3 SBIC P b Skip if Bit in I O Register Cleared if P b 0 PC PC 2 or 3 None 1 2 3 SBIS P b Skip if Bit in I O Register is Set if P b 1 PC PC 2 or 3 None 1 2 3 BRBS s k Branch if Status Flag Set if SREG s 1 then PC PC k 1 None...

Page 161: ... Indirect and Pre Dec Y Y 1 Rd Y None 2 LDD Rd Y q Load Indirect with Displacement Rd Y q None 2 LD Rd Z Load Indirect Rd Z None 2 LD Rd Z Load Indirect and Post Inc Rd Z Z Z 1 None 2 LD Rd Z Load Indirect and Pre Dec Z Z 1 Rd Z None 2 LDD Rd Z q Load Indirect with Displacement Rd Z q None 2 LDS Rd k Load Direct from SRAM Rd k None 2 ST X Rr Store Indirect X Rr None 2 ST X Rr Store Indirect and Po...

Page 162: ...ecification at 125 C Speed MHz Power Supply V Ordering Code 1 Package 2 Operation Range 20 1 8 5 5 ATtiny13A PU ATtiny13A SU ATtiny13A SUR ATtiny13A SH ATtiny13A SHR ATtiny13A SSU ATtiny13A SSUR ATtiny13A SSH ATtiny13A SSHR ATtiny13A MU ATtiny13A MUR ATtiny13A MMU 3 ATtiny13A MMUR 3 8P3 8S2 8S2 8S2 8S2 8S1 8S1 8S1 8S1 20M1 20M1 10M1 3 10M1 3 Industrial 40 C to 85 C 4 ATtiny13A SN ATtiny13A SNR ATt...

Page 163: ... measured with the package seated in JEDEC seating plane Gauge GS 3 3 D D1 and E1 dimensions do not include mold Flash or protrusions Mold Flash or protrusions shall not exceed 0 010 inch 4 E and eA measured with the leads constrained to be perpendicular to datum 5 Pointed or rounded lead tips are preferred to ease insertion 6 b2 and b3 maximum dimensions do not include Dambar protrusions Dambar p...

Page 164: ... EIAJ Drawing EDR 7320 for additional information 2 Mismatch of the upper and lower dies and resin burrs aren t included 3 Determines the true geometric position 4 Values b C apply to plated terminal The standard thickness of the plating layer shall measure between 0 007 to 021 mm A 1 70 2 16 A1 0 05 0 25 b 0 35 0 48 4 C 0 15 0 35 4 D 5 13 5 35 E1 5 18 5 40 2 E 7 70 8 26 L 0 51 0 85 θ 0 8 e 1 27 B...

Page 165: ...Plastic Gull Wing Small Outline JEDEC SOIC 8S1 B H 1 2 N 3 Top View C E End View A B L A2 e D Side View 4 COMMON DIMENSIONS Unit of Measure mm SYMBOL MIN NOM MAX NOTE This drawing is for general information only Refer to JEDEC Drawing MS 012 for proper dimensions tolerances datums etc A 1 75 B 0 51 C 0 25 D 5 00 E 4 00 e 1 27 BSC H 6 20 L 1 27 ...

Page 166: ...Lead Frame Package MLF A 0 70 0 75 0 80 A1 0 01 0 05 A2 0 20 REF b 0 18 0 23 0 30 D 4 00 BSC D2 2 45 2 60 2 75 E 4 00 BSC E2 2 45 2 60 2 75 e 0 50 BSC L 0 35 0 40 0 55 SIDE VIEW Pin 1 ID Pin 1 Notch 0 20 R BOTTOM VIEW TOP VIEW Note Reference JEDEC Standard MO 220 Fig 1 SAW Singulation WGGD 5 COMMON DIMENSIONS Unit of Measure mm SYMBOL MIN NOM MAX NOTE D E e A2 A1 A D2 E2 0 08 C L 1 2 3 b 1 2 3 ...

Page 167: ... 10M1 7 7 06 COMMON DIMENSIONS Unit of Measure mm SYMBOL MIN NOM MAX NOTE A 0 80 0 90 1 00 A1 0 00 0 02 0 05 b 0 18 0 25 0 30 D 2 90 3 00 3 10 D1 1 40 1 75 E 2 90 3 00 3 10 E1 2 20 2 70 e 0 50 L 0 30 0 50 y 0 08 K 0 20 Pin 1 ID TOP VIEW D E A1 A SIDE VIEW BOTTOM VIEW D1 E1 L b e K 1 2 Notes 1 This package conforms to JEDEC reference MO 229C Variation VEED 5 2 The terminal 1 ID is a Lasser marked F...

Page 168: ...M can not be written below 1 9 Volt 1 EEPROM can not be written below 1 9 Volt Writing the EEPROM at VCC below 1 9 volts might fail Problem Fix Workaround Do not write the EEPROM when VCC is below 1 9 volts 24 2 ATtiny13A Rev E F These device revisions were not sampled 24 3 ATtiny13 Rev A D These device revisions were referred to as ATtiny13 ATtiny13V ...

Page 169: ...rtup up Times Table 6 5 and Table 6 6 on page 26 2 Added addresses in all Register Description tables and cross references to Register Summary 3 Updated naming convention for COM bits in tables from Table 11 2 on page 70 to Table 11 7 on page 72 4 Updated value for tWD_ERASE in Table 17 8 Minimum Wait Delay Before Writing the Next Flash or EEPROM Location on page 108 5 Added NiPdAU note for SH and...

Page 170: ...n page 122 6 Added description of new function Power Reduction Register Added functional description on page 31 Added bit description on page 34 Added section Supply Current of I O Modules on page 124 Updated Register Summary on page 158 7 Added description of new function Software BOD Disable Added functional description on page 31 Updated section on page 32 Added register description on page 33 ...

Page 171: ...10 4 5 Stack Pointer 11 4 6 Instruction Execution Timing 12 4 7 Reset and Interrupt Handling 12 5 Memories 15 5 1 In System Reprogrammable Flash Program Memory 15 5 2 SRAM Data Memory 15 5 3 EEPROM Data Memory 16 5 4 I O Memory 20 5 5 Register Description 20 6 System Clock and Clock Options 23 6 1 Clock Systems and their Distribution 23 6 2 Clock Sources 24 6 3 System Clock Prescaler 26 6 4 Regist...

Page 172: ...9 10 2 Ports as General Digital I O 50 10 3 Alternate Port Functions 54 10 4 Register Description 57 11 8 bit Timer Counter0 with PWM 59 11 1 Features 59 11 2 Overview 59 11 3 Timer Counter Clock Sources 60 11 4 Counter Unit 60 11 5 Output Compare Unit 61 11 6 Compare Match Output Unit 63 11 7 Modes of Operation 64 11 8 Timer Counter Timing Diagrams 68 11 9 Register Description 70 12 Timer Counter...

Page 173: ... 96 15 1 Features 96 15 2 Overview 96 15 3 Physical Interface 96 15 4 Software Break Points 97 15 5 Limitations of debugWIRE 97 15 6 Register Description 97 16 Self Programming the Flash 98 16 1 Performing Page Erase by SPM 98 16 2 Filling the Temporary Buffer Page Loading 98 16 3 Performing a Page Write 99 16 4 Addressing the Flash During Self Programming 99 16 5 EEPROM Write Prevents Writing to ...

Page 174: ... Serial Programming Characteristics 123 19 Typical Characteristics 124 19 1 Supply Current of I O Modules 124 19 2 Current Consumption in Active Mode 125 19 3 Current Consumption in Idle Mode 128 19 4 Current Consumption in Power down Mode 131 19 5 Current Consumption in Reset 132 19 6 Current Consumption of Peripheral Units 133 19 7 Pull up Resistors 135 19 8 Output Driver Strength Low Power Pins...

Page 175: ...Errata 168 24 1 ATtiny13A Rev G H 168 24 2 ATtiny13A Rev E F 168 24 3 ATtiny13 Rev A D 168 25 Datasheet Revision History 169 25 1 Rev 8126F 05 12 169 25 2 Rev 8126E 07 10 169 25 3 Rev 8126D 11 09 169 25 4 Rev 8126C 09 09 169 25 5 Rev 8126B 11 08 169 25 6 Rev 8126A 05 08 169 ...

Page 176: ... STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTY OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRINGEMENT IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT INDIRECT CONSEQUENTIAL PUNITIVE SPECIAL OR INCIDEN TAL DAMAGES INCLUDING WITHOUT LIMITATION DAMAGES FOR LOSS OF PROFITS BUSINESS INTERRUPTION OR LOSS OF INFORMATION ARISING OUT OF THE ...

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