Atmel ATmega128RFR2 Manual Download Page 9

    

    

    

    

    

    

    

 

   

 

 

 

 

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8393CS-MCU Wireless-09/14 

ATmega256/128/64RFR2 

 

4 Application Circuits 

4.1 Basic Application Schematic 

A basic application schematic of the ATmega256/128/64RFR2 with a single-ended RF 
connector is shown in 

Figure 4-1 below

 and the associated Bill of Material in 

Table 4-1 

on page 10

. The 50

 single-ended RF input is transformed to the 100

 differential RF 

port impedance using Balun B1. The capacitors C1 and C2 provide AC coupling of the 
RF input to the RF port, capacitor C4 improves matching. 

Figure 4-1.

 Basic Application schematic (64-pin package) 

8

7

6

5

4

3

2

1

17

18

19

20

21

22

23

24

56

57

58

59

60

61

62

63

A

R

E

F

A

V

S

S

AVSS

RFP

RFN

AVSS

TST

D

V

S

S

D

V

D

D

D

V

D

D

X

T

A

L

2

D

E

V

D

D

D

V

S

S

A

V

D

D

E

V

D

D

A

V

S

S

X

T

A

L

1

41

42

43

44

45

46

47

48

PB0

DVSS

PE0

PB7

CB3

CB4

RSTN

V

DD

XTAL

CX1

CX2

CB1

V

DD

CB2

C1

C2

B1

RF

C4

25

26

27

28

29

30

31

32

16

14

13

12

11

10

9

15

64

54

55

49

50

51

52

53

33

34

35

36

37

38

39

40

RSTON

XTAL

32kHz

CX3

CX4

CLKI

DEVDD

DVSS

DEVDD

P

E

7

D

V

S

S

D

E

V

D

D

P

F

0

PF7

PG0

P

G

5

P

D

0

P

D

7

Pins TST & CLKI 
must be connected

 

The power supply bypass capacitors (CB2, CB4) are connected to the external analog 
supply pin (EVDD, pin 59) and external digital supply pin (DEVDD, pin 23). Pins 34, 44 
and 54 supply the digital port pins. 

Floating  pins  can  cause  excessive  power  dissipation  (e.g.  during  power  on).  They 
should be connected to an appropriate source. GPIO shall not be connected to ground 
or power supply directly. 

The digital input pins TST and CLKI must be connected. If pin TST will never be used it 
can be connected to AVSS while an unused pin CLKI could be connected to DVSS (see 
chapter 

"Unused Pins" on page 7

)

Capacitors  CB1  and  CB3  are  bypass  capacitors  for  the  integrated  analog  and  digital 
voltage  regulators  to  ensure  stable  operation  and  to  improve  noise  immunity. 

Summary of Contents for ATmega128RFR2

Page 1: ...al Interface Two Programmable Serial USART Byte Oriented 2 wire Serial Interface Advanced Interrupt Handler and Power Save Modes Watchdog Timer with Separate On Chip Oscillator Power on Reset and Low...

Page 2: ...fter the device is characterized 1 PF3 ADC3 DIG4 PF2 ADC2 DIG2 2 3 PF5 ADC5 TMS PF4 ADC4 TCK 4 5 PF7 ADC7 TDI PF6 ADC6 TDO 6 7 RFP AVSS_RFP 8 9 AVSS_RFN RFN 10 11 RSTN TST 12 13 14 RSTON PG0 DIG3 56 5...

Page 3: ...re combines a rich instruction set with 32 general purpose working registers All 32 registers are directly connected to the Arithmetic Logic Unit ALU Two independent registers can be accessed with one...

Page 4: ...rupt or hardware reset In Power save mode the asynchronous timer continues to run allowing the user to maintain a timer base while the rest of the device is sleeping The ADC Noise Reduction mode stops...

Page 5: ...ted digital supply voltage internally generated 3 2 5 DVSS Digital ground 3 2 6 AVSS Analog ground 3 2 7 Port B PB7 PB0 Port B is an 8 bit bi directional I O port with internal pull up resistors selec...

Page 6: ...Port G pins that are externally pulled low will source current if the pull up resistors are activated The Port G pins are tri stated when a reset condition becomes active even if the clock is not runn...

Page 7: ...4 Configuration summary According to the application requirements a variable memory size allows to optimize current consumption and leakage current Table 3 1 Memory Configuration Device Flash EEPROM S...

Page 8: ...nterface The alternate pin function External Memory interface using Port A and Port C is not implemented due to the missing ports The large internal data memory SRAM does not require an external memor...

Page 9: ...DD CB2 C1 C2 B1 RF C4 25 26 27 28 29 30 31 32 16 14 13 12 11 10 9 15 64 54 55 49 50 51 52 53 33 34 35 36 37 38 39 40 RSTON XTAL 32kHz CX3 CX4 CLKI DEVDD DVSS DEVDD PE7 DVSS DEVDD PF0 PF7 PG0 PG5 PD0 P...

Page 10: ...layout of the PCB and any leakage path must be avoided Crosstalk and radiation from switching digital signals to the crystal pins or the RF pins can degrade the system performance The programming of...

Page 11: ...F AVSS AVSS RFP RFN AVSS TST DVSS DVDD DVDD XTAL2 DEVDD DVSS AVDD EVDD AVSS XTAL1 41 42 43 44 45 46 47 48 PB0 DVSS PE0 PB7 CB3 CB4 RSTN VDD XTAL CX1 CX2 CB1 VDD CB2 25 26 27 28 29 30 31 32 16 14 13 12...

Page 12: ...re referring to this document The referring revision in this section are referring to the document revision Rev 8393CS MCU Wireless 09 14 1 Content unchanged recreated for combined release with the da...

Page 13: ...ns 2 2 Disclaimer 2 3 Overview 3 3 1 Block Diagram 3 3 2 Pin Descriptions 5 3 3 Unused Pins 7 3 4 Configuration summary 7 3 5 Compatibility to ATmega1281 2561 8 4 Application Circuits 9 4 1 Basic Appl...

Page 14: ...tion with the sale of Atmel products EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS IMPLIED...

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