Atmel ATmega128RFR2 Manual Download Page 10

    

    

    

    

    

    

    

 

 

 

 

 

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8393CS-MCU Wireless-09/14

ATmega256/128/64RFR2 

 

Capacitors  should  be  placed  as  close  as  possible  to  the  pins  and  should  have  a  low-
resistance and low-inductance connection to ground to achieve the best performance. 

The  crystal  (XTAL),  the  two  load  capacitors  (CX1,  CX2),  and  the  internal  circuitry 
connected to pins XTAL1 and XTAL2 form the 16MHz crystal oscillator for the 2.4GHz 
transceiver. To achieve the best accuracy and stability of the reference frequency, large 
parasitic  capacitances  must  be  avoided.  Crystal  lines  should  be  routed  as  short  as 
possible  and  not  in  proximity  of  digital  I/O  signals.  This  is  especially  required  for  the 
High Data Rate Modes. 

The 32.768 kHz crystal connected to the internal low power (sub 1

µ

A) crystal oscillator 

provides a stable time reference for all low power modes including 32 Bit IEEE 802.15.4 
Symbol  Counter  (

"MAC  Symbol  Counter"

)  and  real  time  clock  application  using  the 

asynchronous  timer  T/C2  (

"Timer/Counter2  with  PWM  and  Asynchronous  Operation"

). 

Total shunt capacitance including CX3, CX4 should not exceed 15pF across both pins. 
The very low supply current of the oscillator requires careful layout of the PCB and any 
leakage path must be avoided. 

Crosstalk and radiation from switching digital signals to the crystal pins or the RF pins 
can  degrade  the  system  performance.  The  programming  of  minimum  drive  strength 
settings  for  the  digital  output  signal  is  recommended  (see 

"DPDS0  -  Port  Driver 

Strength Register 0"

). 

Table 4-1.

 Bill of Materials (BoM) 

Designator 

Description 

Value 

Manufacturer 

Part Number 

Comment 

B1 

SMD balun 

SMD balun / filter 

2.4 GHz 

Wuerth 

Johanson 

Technology 

748421245 

2450FB15L0001 

 

 

Filter included 

 

CB1 

CB3 

LDO VREG  

bypass capacitor 

µ

(100nF minimum) 

AVX 

Murata 

0603YD105KAT2A 

GRM188R61C105KA12D 

X5R  

(0603) 

10% 

16V 

CB2 

CB4 

Power supply bypass 

capacitor 

µ

(100nF minimum) 

CX1, CX2 

 

16MHz crystal load 
capacitor 

12 pF 

 

AVX 

Murata 

06035A120JA 

GRP1886C1H120JA01 

COG 

(0603) 

5% 

50V 

CX3, CX4 

32.768kHz crystal load 
capacitor 

12 … 25 pF 

 

 

 

 

 

C1, C2 

 

RF coupling capacitor 

 

22 pF 

 

Epcos 

Epcos 

AVX 

B37930 

B37920 

06035A220JAT2A 

C0G 

5% 

50V 

(0402 or 0603) 

C4 (optional)  RF matching 

0.47 pF 

Johnstech 

 

 

 

 

XTAL 

Crystal 

CX-4025 16 MHz 

SX-4025 16 MHz 

ACAL Taitjen 

Siward 

XWBBPL-F-1 

A207-011 

 

XTAL 32kHz  Crystal 

 

 

 

Rs=100 kOhm 

 

4.2 Extended Feature Set Application Schematic 

The ATmega256/128/64RFR2 supports additional features like: 

  Security Module (AES) 

  High Data Rate Mode up to 2MBits/s 

  Antenna Diversity using alternate pin function DIG1/2 at Port G and F 

Summary of Contents for ATmega128RFR2

Page 1: ...al Interface Two Programmable Serial USART Byte Oriented 2 wire Serial Interface Advanced Interrupt Handler and Power Save Modes Watchdog Timer with Separate On Chip Oscillator Power on Reset and Low...

Page 2: ...fter the device is characterized 1 PF3 ADC3 DIG4 PF2 ADC2 DIG2 2 3 PF5 ADC5 TMS PF4 ADC4 TCK 4 5 PF7 ADC7 TDI PF6 ADC6 TDO 6 7 RFP AVSS_RFP 8 9 AVSS_RFN RFN 10 11 RSTN TST 12 13 14 RSTON PG0 DIG3 56 5...

Page 3: ...re combines a rich instruction set with 32 general purpose working registers All 32 registers are directly connected to the Arithmetic Logic Unit ALU Two independent registers can be accessed with one...

Page 4: ...rupt or hardware reset In Power save mode the asynchronous timer continues to run allowing the user to maintain a timer base while the rest of the device is sleeping The ADC Noise Reduction mode stops...

Page 5: ...ted digital supply voltage internally generated 3 2 5 DVSS Digital ground 3 2 6 AVSS Analog ground 3 2 7 Port B PB7 PB0 Port B is an 8 bit bi directional I O port with internal pull up resistors selec...

Page 6: ...Port G pins that are externally pulled low will source current if the pull up resistors are activated The Port G pins are tri stated when a reset condition becomes active even if the clock is not runn...

Page 7: ...4 Configuration summary According to the application requirements a variable memory size allows to optimize current consumption and leakage current Table 3 1 Memory Configuration Device Flash EEPROM S...

Page 8: ...nterface The alternate pin function External Memory interface using Port A and Port C is not implemented due to the missing ports The large internal data memory SRAM does not require an external memor...

Page 9: ...DD CB2 C1 C2 B1 RF C4 25 26 27 28 29 30 31 32 16 14 13 12 11 10 9 15 64 54 55 49 50 51 52 53 33 34 35 36 37 38 39 40 RSTON XTAL 32kHz CX3 CX4 CLKI DEVDD DVSS DEVDD PE7 DVSS DEVDD PF0 PF7 PG0 PG5 PD0 P...

Page 10: ...layout of the PCB and any leakage path must be avoided Crosstalk and radiation from switching digital signals to the crystal pins or the RF pins can degrade the system performance The programming of...

Page 11: ...F AVSS AVSS RFP RFN AVSS TST DVSS DVDD DVDD XTAL2 DEVDD DVSS AVDD EVDD AVSS XTAL1 41 42 43 44 45 46 47 48 PB0 DVSS PE0 PB7 CB3 CB4 RSTN VDD XTAL CX1 CX2 CB1 VDD CB2 25 26 27 28 29 30 31 32 16 14 13 12...

Page 12: ...re referring to this document The referring revision in this section are referring to the document revision Rev 8393CS MCU Wireless 09 14 1 Content unchanged recreated for combined release with the da...

Page 13: ...ns 2 2 Disclaimer 2 3 Overview 3 3 1 Block Diagram 3 3 2 Pin Descriptions 5 3 3 Unused Pins 7 3 4 Configuration summary 7 3 5 Compatibility to ATmega1281 2561 8 4 Application Circuits 9 4 1 Basic Appl...

Page 14: ...tion with the sale of Atmel products EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS IMPLIED...

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