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AT91SAM-ICE User Guide
6206B–ATARM–04-Mar-08
Host
A computer which provides data and other services to another computer. Especially, a computer provid-
ing debugging services to a target being debugged.
ICache
Instruction cache.
ICE Extension Unit
A hardware extension to the EmbeddedICE logic that provides more breakpoint units.
ID
Identifier.
IEEE 1149.1
The IEEE Standard which defines TAP. Commonly (but incorrectly) referred to as JTAG.
Image
An executable file that has been loaded onto a processor for execution.
In-Circuit Emulator (ICE)
A device enabling access to and modification of the signals of a circuit while that circuit is operating.
Instruction Register
When referring to a TAP controller, a register that controls the operation of the TAP.
IR
See Instruction Register.
Joint Test Action Group (JTAG)
The name of the standards group which created the IEEE 1149.1 specification.
Little-endian
Memory organization where the least significant byte of a word is at a lower address than the most signif-
icant byte. See also Big-endian.
Memory Management Unit (MMU)
Hardware that controls caches and access permissions to blocks of memory, and translates virtual to
physical addresses.
Multi-ICE
®
Multi-processor EmbeddedICE interface. ARM
®
registered trademark.
nSRST
Abbreviation of System Reset. The electronic signal which causes the target system other than the TAP
controller to be reset. This signal is known as nSYSRST in some other manuals. See also nTRST.
nTRST
Abbreviation of TAP Reset. The electronic signal that causes the target system TAP controller to be
reset. This signal is known as nICERST in some other manuals. See also nSRST.
