7
0368G–MICRO–6/05
AT89C2051
9.
Idle Mode
In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The
mode is invoked by software. The content of the on-chip RAM and all the special functions regis-
ters remain unchanged during this mode. The idle mode can be terminated by any enabled
interrupt or by a hardware reset.
The P1.0 and P1.1 should be set to “0” if no external pull-ups are used, or set to “1” if
external pull-ups are used.
It should be noted that when idle is terminated by a hardware reset, the device normally
resumes program execution, from where it left off, up to two machine cycles before the internal
reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but
access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a
port pin when Idle is terminated by reset, the instruction following the one that invokes Idle
should not be one that writes to a port pin or to external memory.
10. Power-down Mode
In the power-down mode the oscillator is stopped, and the instruction that invokes power-down
is the last instruction executed. The on-chip RAM and Special Function Registers retain their
values until the power-down mode is terminated. The only exit from power-down is a hardware
reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be
activated before V
CC
is restored to its normal operating level and must be held active long
enough to allow the oscillator to restart and stabilize.
The P1.0 and P1.1 should be set to “0” if no external pull-ups are used, or set to “1” if
external pull-ups are used.
11. Programming The Flash
The AT89C2051 is shipped with the 2K bytes of on-chip PEROM code memory array in the
erased state (i.e., contents = FFH) and ready to be programmed. The code memory array is pro-
grammed one byte at a time.
Once the array is programmed, to re-program any non-blank byte,
the entire memory array needs to be erased electrically.
Internal Address Counter:
The AT89C2051 contains an internal PEROM address counter
which is always reset to 000H on the rising edge of RST and is advanced by applying a positive
going pulse to pin XTAL1.
Programming Algorithm:
To program the AT89C2051, the following sequence is
recommended.
1.
Power-up sequence:
Apply power between V
CC
and GND pins
Set RST and XTAL1 to GND
2.
Set pin RST to “H”
Set pin P3.2 to “H”
3.
Apply the appropriate combination of “H” or “L” logic
levels to pins P3.3, P3.4, P3.5, P3.7 to select one of the programming operations
shown in the PEROM Programming Modes table.
Summary of Contents for AT89C2051
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