Atmel AT32UC3A3128, Manual

Page: 342 / 1021

342
32072H–AVR32–10/2012
AT32UC3A3
Reg.CH_EN) bit until it is cleared by hardware, to detect when the transfer is complete.
If the DMACA is not in Row 1, the next step is performed.
7. The DMA transfer proceeds as follows:
a. If interrupts are enabled (CTLx.INT_EN = 1) and the block complete interrupt is un-
masked (MaskBlock[x] = 1’b1, where x is the channel number) hardware sets the
block complete interrupt when the block transfer has completed. It then stalls until
the block complete interrupt is cleared by software. If the next block is to be the last
block in the DMA transfer, then the block complete ISR (interrupt service routine)
should clear the source reload bit, CFGx.RELOAD_SR. This puts the DMACA into
Row1 as shown in
Table 19-1 on page 327 . If the next block is not the last block in
the DMA transfer then the source reload bit should remain enabled to keep the
DMACA in Row3 as shown in
Table 19-1 on page 327 .
b. If interrupts are disabled (CTLx.INT_EN = 0) or the block complete interrupt is
masked (MaskBlock[x] = 1’b0, where x is the channel number) then hardware does
not stall until it detects a write to the block complete interrupt clear register but
starts the next block transfer immediately. In this case software must clear the
source reload bit, CFGx.RELOAD_SR, to put the device into ROW 1 of
Table 19-1
on page 327 before the last block of the DMA transfer has completed.
The transfer is similar to that shown in Figure 19-15 on page 342 .
The DMA Transfer flow is shown in Figure 19-16 on page 343 .
Figure 19-15. Multi-block Transfer with Source Address Auto-reloaded and Contiguous Desti-
nation Address
Address of
Source Layer
Address of
Destination Layer
Source Blocks
Destination Blocks
SAR
Block0
Block1
Block2
DAR(1)
DAR(0)
DAR(2)