343
32072H–AVR32–10/2012
AT32UC3A3
Figure 19-16. DMA Transfer for Source Address Auto-reloaded and Contiguous Destination
Address
19.10.1.6
Multi-block DMA Transfer with Linked List for Source and Contiguous Destination Address (Row 8)
1.
Read the Channel Enable register to choose a free (disabled) channel.
2.
Set up the linked list in memory. Write the control information in the LLI. CTLx register
location of the block descriptor for each LLI in memory for channel x. For example, in
the register, you can program the following:
a.
Set up the transfer type (memory or non-memory peripheral for source and desti-
nation) and flow control device by programming the TT_FC of the CTLx register.
b.
Set up the transfer characteristics, such as:
– i. Transfer width for the source in the SRC_TR_WIDTH field.
– ii. Transfer width for the destination in the DST_TR_WIDTH field.
– iii. Source master layer in the SMS field where source resides.
– iv. Destination master layer in the DMS field where destination resides.
Channel Enabled by
software
Block Transfer
Reload SARx, CTLx
Channel Disabled by
hardware
Block Complete interrupt
generated here
DMAC Transfer Complete
interrupt generated here
yes
no
no
yes
Stall until Block Complete
interrupt cleared by software
CTLx.INT_EN=1
&&
MASKBLOCK[x]=1?
Is DMAC in Row1 of
DMAC State Machine Table?
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Page 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...
