Hardware Description
2-8
AT18F-DK3 Configurator Development Kit User Guide
3685A–CNFG–04/08
The ISP algorithm is controlled by the JCPS (JTAG Configurator Programming System) software, which
is running on the PC. The four JTAG signals are generated by the LPT port and they are buffered by the
ISP download cable before going into the ATF15xx-DK3 Base Board of the AT18F-DK3 kit. The pinout
for the 10-pin JTAG Port Header on the ATF15xx-DK3 Base Board is shown in
and the
dimensions of this 10-pin male JTAG header are shown in
Figure 2-8.
Pinout Diagram of 10-pin JTAG Port Header (Top-view)
Figure 2-9.
10-pin Male Header Dimensions
Notes:
1. All dimensions are in inches.
2. Pitch = 1-inch = 2.54 mm
2
4
6
8
10
1
3
5
7
9
GND
NC
NC
VCC
GND
TDI
NC
TMS
TDO
TCK
Top View
S
ide View
0.100
0.025
Sq
.
0.2
3
5
0.100
