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Atmal FPSLIC STK594, User Manual

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Atmal FPSLIC STK594 User Manual Download Page 26

Using System Designer

FPSLIC STK594 User Guide

4-11

2819D–FPSLI–11/04

4.8

FPGA Place and 
Route

The Figaro Integrated Development System (IDS) is used as the FPGA Place & Route
tool. Figaro takes the gate-level technology-specific file generated by the synthesis tool
and partitions, places, and routes the FPGA design.

1.

Press the Figaro IDS button to open the FPGA Place & Route Tools Settings dia-
log, see Figure 4-15.

Figure 4-15.  FPGA Place & Route Tools Settings Dialog

2.

Select Open EDIF Netlist and Browse to select 

COUNTER.edf

, then press OK. 

Figaro should open and complete the Open, Map, and Parts steps automatically, 
once completed the Figaro Batch Options dialog appears, see Figure 4-16.

Figure 4-16.  Figaro Batch Options Dialog

The Figaro Batch Options allows for the setting of various Figaro FPGA compiler
constraints. This includes I/O Pin Locking, I/O Pad Attributes and Place & Route
quality effort levels.

Summary of Contents for FPSLIC STK594

Page 1: ...FPSLIC STK594 User Guide ...

Page 2: ...t 2 4 2 7 Two Wire Serial Interface TWSI 2 5 2 7 1 Description of Configuration Memory Pins 2 5 2 8 External Interrupts 2 5 2 9 Split Power Supply Support 2 6 2 10 XTAL Switch 2 6 2 11 Reset Switches 2 6 Section 3 Installing System Designer 3 1 3 1 System Requirements 3 1 3 3 Configuration Programming System CPS Installation 3 2 3 4 System Designer Licensing 3 2 3 4 1 Requesting a System Designer ...

Page 3: ...Table of Contents FPSLIC STK594 User Guide ii 2819D FPSLI 11 04 4 10 1 Hardware Setup 4 15 4 10 2 Software Setup 4 16 Section 5 Technical Specifications 5 1 Section 6 Complete Schematics 6 1 ...

Page 4: ...e STK594 includes connectors jumpers and hardware allowing full utilization of the new features of the FPSLIC family see Figure 1 1 This user guide acts as a general getting started guide as well as a complete technical reference for advanced users In addition to adding support for new devices it also adds new support for peripherals previously not supported by the STK500 An additional RS 232 port...

Page 5: ...AVR Studio and System Designer Compatible Supports AT94KAL and AT94KAX Devices Supports all Added Features in FPSLIC Devices JTAG Connector for On chip Debugging Using JTAG ICE Additional RS 232C Port with Available RTS CTS Handshake Lines On board 32 kHz Crystal for Easy RTC Implementations ...

Page 6: ...ge for the AT94K devices Prior to using the STK594 board it is necessary to adjust the VTARGET to a value between 3 0 and 3 6V For more information on adjusting VTARGET from within AVR Studio consult section 5 3 5 1 of the STK500 User Guide available on the Atmel web site www atmel com Note It may be necessary to adjust the VDD voltage see Split Power Supply Support on page 6 of this section for m...

Page 7: ...on the STK500 these ports are located on the STK594 board The STK594 ports have the same pinout and func tionality as the ports on the STK500 board Since Port A to Port D are already present on the STK500 board they are not duplicated on the STK594 2 2 1 PORT E Figure 2 2 shows the pinout for the I O port headers Port E Figure 2 2 General I O Ports Note Port E is also present on the STK500 but onl...

Page 8: ...pic refer to the Code Self Modify application note available on the Atmel web site Note The AT94K devices also support Cache Logic Configuration For more infor mation on this topic refer to the Cache Logic Configuration application note available on the Atmel web site For more details on programming procedures refer to Section 4 10 2 4 JTAG Connector The JTAG connector is intended for the AT94K de...

Page 9: ... Figure 2 6 UART Header 2 6 1 Second RS 232C Port The AT94K device has an additional UART The RS 232 port on the STK594 board has in addition to the RXD and TXD lines support for RTS and CTS flow control Figure 2 7 shows a simplified block schematic on how this is implemented Note The UART in AT94K devices does not support hardware RTS or CTS control If such functionality is needed it must be impl...

Page 10: ...m the Atmel web site The configurator can be connected to the I O pins of the embedded AVR microcontrol ler The 4 pin header marked CONFIG can be used for connecting the TWSI interface of the configurator to the I O pins of the target AVR microcontroller Two wire cables are included with the STK500 for connecting the configurator to the I O pins Figure 2 9 shows the pinout of a header for the Conf...

Page 11: ... to set the jumper to select the core voltage Figure 2 11 AT94K Core Voltage Selector 2 10 XTAL Switch An oscillator is included on the STK594 for supplying an additional clock to the AT94K FPSLIC device The XTAL switch selects if the oscillator is connected to the XTAL1 pin or whether the clock is provided by the STK500 Figure 2 12 shows a simplified block schematic on how this is implemented Fig...

Page 12: ...R design concurrently 3 1 System Requirements For a single user system System Designer requires a personal computer equipped as follows CD ROM Drive 250 Mbyte Minimum Hard Drive 128 Mbyte RAM Parallel Interface Port Windows 95 98 2000 Me or WindowsNT 4 0 Network Interface Card or Security Dongle The software security dongle is used to generate a unique HOSTID for systems without a network interfac...

Page 13: ...nd ATFS series configu ration memories found on the STK594 Note When installing the CPS utility it is necessary to install the software in an account with Administrator privileges if the operating system is WindowsNT or Windows 2000 XP 3 4 System Designer Licensing The licensing of System Designer is for the Mentor Graphics tools You can use System Designer without a valid license however you will...

Page 14: ...a different path and or file name make the necessary changes Note If you are using Windows 95 98 Me it is necessary to reboot the machine prior to running the System Designer software 3 4 3 Testing the System Designer License Once you have configured your license you can test it by invoking the Mentor Graphics programs that require a license 1 Launch ModelSim from Start Programs Atmel ModelTech Mo...

Page 15: ...Installing System Designer 3 4 FPSLIC STK594 User Guide 2819D FPSLI 11 04 ...

Page 16: ...from the FPSLIC software page of the Atmel web site and copy STK594 ZIP to C SystemDesigner Designs 2 Extract the contents of the STK594 ZIP file to C SystemDesigner Designs The contents of the zip file are shown in Table 4 1 Table 4 1 STK594 ZIP File Description AT94KDEF INC Atmel AVR Assembler AT94K FPSLIC Include File COUNTER PIN FPGA Pin Lock File COUNTER V Top Level FPGA Verilog Counter Sourc...

Page 17: ...ill commence and the process will be repeated Figure 4 1 shows a simplified block diagram of the tutorial design Figure 4 1 Tutorial Design Block Diagram 4 3 Design Flow The design presented in this tutorial only performs the required steps for designing and programming an AT94K series device For more information on the optional steps i e Simulation and Co verification please consult the FPSLIC ap...

Page 18: ... 1 Launch System Designer from the desktop icon or by pointing to Start Pro grams Atmel SystemDesigner 2 Create a new project by selecting New from the Project menu and then pressing the New Project Wizard button see Figure 4 3 Figure 4 3 New Project Wizard Window Step 1 of 6 3 Press Next The window to create a project file opens see Figure 4 4 Figure 4 4 New Project Wizard Window Step 2 of 6 ...

Page 19: ...Next The part selection window appears see Figure 4 5 Figure 4 5 New Project Wizard Window Step 3 of 6 5 Select AT94K10AL 25DQC 1 from the parts list as this is the part found on the STK594 development board and press Next The software tool flow window opens see Figure 4 6 Note 1 Some boards use AT94K40AL 25DQC devices Figure 4 6 New Project Wizard Window Step 4 of 6 ...

Page 20: ...ss Next The add parts window opens see Figure 4 7 For this tutorial the instructions will assume Mentor Verilog has been selected Figure 4 7 New Project Wizard Window Step 5 of 6 Figure 4 8 New Project Wizard Window Step 6 of 6 7 Press Finish to exit the New Project Wizard The project window now contains the TUTORIAL design see Figure 4 9 ...

Page 21: ...m Designer 4 6 FPSLIC STK594 User Guide 2819D FPSLI 11 04 Figure 4 9 Project Window 8 From the System Designer desktop click on the Part Graphic see Figure 4 9 to switch to the Design Flow Manager see Figure 4 10 ...

Page 22: ... FPSLIC devices The red and blue arrows show the dependencies between the various stages of development This tutorial will only show the minimum steps in order to complete a design The remainder of the steps involves simulation and co verification For further information on simulation and co verification please consult the Quick Start Tutorial available on the Atmel web site ...

Page 23: ...AVR Studio if assembly was successful Note If assembly was not successful make sure the include file AT94KDEF INC is in the design directory Only AT94K devices with a J label support JTAG ICE debugging For design entry using assembly language consult the AT94K datasheet for a summary of instructions supported by the FPSLIC devices The complete AVR Instruction Set Nomenclature describes each instru...

Page 24: ...pen LeonardoSpectrum opens 5 Leonardo automatically selects Atmel AT94K as the Technology and lists COUNTER V under Input Leonardo also lists COUNTER edf under Output 6 Press Run Flow Figure 4 13 shows a successful synthesis Figure 4 13 Leonardo Spectrum Successful Synthesis 7 Close Leonardo Spectrum when prompted to save your project press No ...

Page 25: ...box 4 Select the LOAD signal from the Input Design Ports and then select IOSELA0 from the AVRIoSelects 5 Press Connect to connect the counter s LOAD signal to FPGA AVR I O Select 0 6 Connect the remaining inputs and outputs as shown in Table 4 2 7 Uncheck Generate Template Test Bench File on the bottom left hand side of the Select Ports dialog Since we are not performing co verification it is not ...

Page 26: ... the FPGA Place Route Tools Settings dia log see Figure 4 15 Figure 4 15 FPGA Place Route Tools Settings Dialog 2 Select Open EDIF Netlist and Browse to select COUNTER edf then press OK Figaro should open and complete the Open Map and Parts steps automatically once completed the Figaro Batch Options dialog appears see Figure 4 16 Figure 4 16 Figaro Batch Options Dialog The Figaro Batch Options all...

Page 27: ...rt Constraints again select IO Pad Attr att from the List files of the Type drop down list and then select the COUNTER ATT and press OK Place and Route a Use the default setting for Quality Quality sets the trade off between Figaro s speed and the efficiency of the Place Route result see the online help for further information b Use the default setting for Timing Driven Design Checking the Timing ...

Page 28: ...ing utility The FPSLIC Control Register Settings dialog opens see Figure 4 17 Figure 4 17 FPSLIC Control Register Settings Dialog 2 Check the Include FPGA Bitstream box and select COUNTER BST by pressing Browse 3 Check the Include AVR Hex File box and select STK594 HEX by pressing Browse 4 Select the FPSLIC Control Register Settings tab and use the default settings see Figure 4 18 5 Be sure to unc...

Page 29: ... OK to generate the combined bitstream file Note It is possible to generate a bitstream for only the FPGA or AVR as you may only want to program that portion of the FPSLIC device To include only the AVR HEX file simply uncheck the Include FPGA Bitstream box Programming only the FPGA portion can be done in a similar fashion ...

Page 30: ...Pro gramming Dongle 2 Connect the 10 pin ISP header on the STK594 to the 10 pin ribbon cable of the ATDH2225 The ATDH2225 is keyed to assure proper orientation see Figure 4 19 Figure 4 19 In System Programming 3 Place the Programming switch in the PROG position 4 Using a 10 wire ribbon cable from the STK500 connect PORTD to the LEDS 5 Using a 2 wire cable from the STK500 connect SW0 and SW1 to FPS...

Page 31: ...BST under Output File 5 Select AT17LV010 A 1M under Device 6 Select Low under Reset Polarity 7 Select AT40K Cypress under FPGA Family 8 Select LPT1 under COMM Port assuming LPT1 is the parallel port connected to the ATDH2225 programming adapter 9 Select Slow under Data Rate 10 Select Low under A2 Bit Level 11 Press Start Procedure When finished a statistics report will be provided in the CPS log w...

Page 32: ...amming Switch to the RUN position for configuration of the FPSLIC device to occur If the LEDs on the STK500 begin to count the configuration has occurred If the configu ration does not occur press the RESET button found on the STK594 board to initiate a configuration download Alternatively power cycling the STK500 will also initiate a configuration download ...

Page 33: ...Using System Designer 4 18 FPSLIC STK594 User Guide 2819D FPSLI 11 04 ...

Page 34: ...LI 11 04 Section 5 Technical Specifications System Unit Physical Dimensions 5 125 x 2 75 Weight 6 oz Operating Conditions Voltage Supply VCC 3 3V VDD 1 8 3 3V Connections Serial Connector 9 pin D SUB Female Serial Communications Speed 250 kbps ...

Page 35: ...Technical Specifications 5 2 FPSLIC STK594 User Guide 2819D FPSLI 11 04 ...

Page 36: ...FPSLIC STK594 User Guide 6 1 Rev 2819D FPSLI 11 04 Section 6 Complete Schematics See the following pages the complete schematics and assembly drawings of the STK594 ...

Page 37: ... C C B B A A CHW5472 ATSTK594 Clock Circuitry Friday April 26 2002 Title A Size Document Number Rev A Date Sheet 1of 6 XTAL1 XTAL2 XT1 XT2 TOSC1 TOSC2 XTAL1 XTAL2 XT1 XT2 TOSC1 TOSC2 C2 27 pF SW1 SW DPDT 2 1 3 5 4 6 SW2 SW DPDT 2 1 3 5 4 6 R2 10M Y2 OSC8 5 OUT C1 33 pF R1 200K Y1 32 768 kHz ...

Page 38: ... I O G N D I O I O TMS I O TCK I O I O I O I O I O I O INIT I O V D D G N D I O I O I O I O I O I O I O I O I O I O G N D I O I O I O I O I O I O I O I O I O GCK4 I O G N D N C C O N N C N C V C C N C R E S E T PE0 PE1 P D 0 P D 1 PE2 P D 2 N C N C N C N C N C P D 3 P D 4 PE3 C S 0 S D A S C L P D 5 P D 6 PE4 PE5 V D D G N D PE6 PE7 CHECK P D 7 INTP0 N C N C X T A L 1 X T A L 2 R X 0 T X 0 G N D N...

Page 39: ...T2 PCM2 RST PBM 7 0 GND DSOT PAT6 GND AUX_O0 PDT 7 0 PAT 7 0 TDO VTG VTG GND PAT3 PAT5 PCT3 RX1 PBT2 GND PET1 PCM5 PCM 7 0 PBT1 PAT4 XT2 AUX_I1 AUX_O 1 0 AUX_I 1 0 TOSC1 CTS RXD TXD RTS PET 7 0 PET 2 0 PCM 7 0 PCT 7 0 PAT 7 0 PDT 7 0 PBT 7 0 PBM 7 0 TOSC2 TOSC1 SCL SDA RST TCK TDO TMS TDI AUX_I 1 0 AUX_O 1 0 cSCL CTS cSDA cSER_EN DSOT DCST XT2 DSIT DCKT XT1 VADJ RST AREFT INTP1 INTP3 INTP0 INTP2 T...

Page 40: ...cument Number Rev A Friday April 26 2002 Date Sheet 4 of 6 CON RESET VCC GND cSCL INIT D0 SER_EN CCLK cSER_EN cSDA cSDA RESET cSCL INIT cSER_EN CON VCC VCC VCC VCC SW4 C15 0 1 uF SW3 SW 4PDT 11 6 5 4 12 3 9 8 2 1 7 10 U2 AT17LV010 LAP 1 2 3 4 6 7 DATA CLK RESET OE CE CEO SER_EN D1 1N4001 1 2 R5 2K7 R7 4K7 C14 0 003 uF J14 CON10A 1 3 5 7 9 2 4 6 8 10 R6 2K7 CCLK D0 ...

Page 41: ... B B A A GND VCC VDD VOUT VCC VDD VCC VOUT VCC VDD VOUT TP1 T POINT F 1 J15 CON3 1 2 3 C16 10 uF TP2 T POINT F 1 TP3 T POINT F 1 C17 10 uF U3 LT1117 1 8 SOT 1 2 3 ADJ GND VOUT VIN A STK594 Split Power Rail Circuitry Title Size CHW5472 Document Number Rev A Friday April 26 2002 Date Sheet 5 of 6 ...

Page 42: ... RXD TXD RTS VCC VCC C22 0 1 uF U4 MAX3232 13 8 10 11 1 3 4 5 2 6 12 9 14 7 R1IN R2IN T2IN T1IN C1 C1 C2 C2 V V R1OUT R2OUT T1OUT T2OUT P1 CONNECTOR DB9 5 9 4 8 3 7 2 6 1 C21 0 1 uF C18 0 1 uF C20 0 1 uF C19 0 1 uF A STK594 RS 232 Spare 2 Circuitry Title Size CHW5472 Document Number Rev A Friday April 26 2002 Date Sheet 6 of 6 ...

Page 43: ...Complete Schematics 6 8 FPSLIC STK594 User Guide 2819D FPSLI 11 04 ...

Page 44: ...26 426 5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel 852 2721 9778 Fax 852 2722 1369 Japan 9F Tonetsu Shinkawa Bldg 1 24 8 Shinkawa Chuo ku Tokyo 104 0033 Japan Tel 81 3 3523 3551 Fax 81 3 3523 7581 Memory 2325 Orchard Parkway San Jose CA 95131 USA Tel 1 408 441 0311 Fax 1 408 436 4314 Microcontrollers 2325 Orchard Parkway San Jose CA 95131 USA Tel ...

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