Atmal FPSLIC STK594, User Manual

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Using System Designer
4-2 FPSLIC STK594 User Guide
2819D–FPSLI–11/04
4.2 Description
The design in this tutorial is composed of a simple AVR
®
microcontroller program and a
loadable counter implemented in the FPGA. When the counter reaches the terminal
value, an interrupt to the microcontroller will be generated using the counter’s carry-out
(RCO) signal. The interrupt is active Low and must be held for three clock cycles prior to
its acknowledgement by the microcontroller. During the Interrupt Service Routine (ISR)
the microcontroller increments the count of interrupt occurrences and places the incre-
mented data on PORTD and the AVR-FPGA Data Bus, triggering the counter’s LOAD
signal. Once the counter has been loaded, counting will commence and the process will
be repeated. Figure 4-1 shows a simplified block diagram of the tutorial design.
Figure 4-1. Tutorial Design Block Diagram
4.3 Design Flow
The design presented in this tutorial, only performs the required steps for designing and
programming an AT94K series device. For more information on the optional steps (i.e.
Simulation and Co-verification) please consult the FPSLIC application notes available
on the Atmel web site. Figure 4-2 outlines the design flow followed in this tutorial. For
more information on a specific step, consult the appropriate section within this tutorial.
Figure 4-2. Design Flow
IOSELA0
IOSEL A0
INTA0
GCLK5
AVR
Microcontroller
FPGA Interrupt 0
Global Clock 5
LOAD
ENABLE
D[7:0]
RESET
Q
RCO
CLOCK
AVR Data Bus 8-bit
FPGA
8-bit Counter
FIOWEA
aWE
AVR Write Enable
FPGA I/O SELECT 0
PORTD
Microcontroller
Assembly
HDL Synthesis
AVR <> FPGA
Interface
FPGA
Place & Route
Bitstream
Generation