ATI Audio Inc.
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Tel: 856-626-3480
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Fax: 856-504-0220
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www.
audio.com
• Switchable re-clocking regenerates stable data before distribution
• Loop thru transformer balanced and isolated inputs
• Switchable input termination
• Individual, transformer balanced and isolated 110-ohm XLR outputs (XLR only)
• Individual isolated 75-ohm BNC outputs (BNC only)
• Two front-panel-selectable inputs
• Six outputs
• Front panel control locking system
• Quiet, internal linear power supply
• Attractive and rugged 1RU package
DESCRIPTION
INPUTS
Incoming AES/EBU formatted digital audio data is selected by the front panel
Input Select switch and applied to the input transformer. Both XLR and BNC
inputs are balanced and DC isolated from ground. Input termination resistors at
75 ohms for BNC inputs or 110 ohms for XLR inputs can be switched in or out of
the circuit with the front panel Input Term switch. Inputs should always be
terminated unless they are looped thru to another device or DDA input. The last
device or input should always terminate the line.
INPUT EQUALIZERS
The input signals feed automatic cable equalizer circuits. Input equalization
should only be necessary for extremely long input cable lengths and should only
be used if proven to be necessary. Automatic equalization is enabled by pressing
the front panel button labeled Input EQ. The automatic equalizer provides only
the minimum amount of boost required to compensate for excess cable roll-off to
avoid over-equalization, which can degrade noise margins.
RECEIVERS
When input re-clocking is enabled, the equalized AES/EBU data stream is
applied to the receiver circuit which recovers the clock and synchronization
signals and separates the audio and digital data. The audio data may be 16 to 24
bits at sample rates from 27 to 192 kHz.
Frame sync (FSYNC), Serial Clock (SCK), Serial audio data (SDATA), Channel
status (C), User channel data (U), and data validity information (VERF) are
passed directly to the transmitter section for reformatting into the output data
stream. VERF is an OR’ing of the validity information from the incoming data (V)
with an internal error flag (ERF) that detects serious transmission errors such as
parity errors, bi-phase coding violations and an out-of-lock PLL receiver. Errors
are displayed on the front panel to aid in troubleshooting. VERF then becomes
the transmitted validity bit (V) and can be used by downstream error correction
devices to interpolate through errors.