Asus AAEON GENE-CML5 User Manual Download

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Chapter 2

–

Hardware Information

3.5

” S

mp
act

ard

ENE

-C

ML5

2.4.15 LVDS Port Inverter/ Backlight Connector (CN18)

Pin Name

Signal Type

Signal level

+VCC_LVDS_BKLT

PWR

+VCC_LVDS_BKLT

PWR

L_BKLTNESS

I/O

GND

LVDS_BKLTEN

I/O

Note 1: LVDS Backlight VCC can be by JP1. (See Ch 2.3.2)

Note 2: Backlight ConVCC_LVDS_BKLT max driving current is 1.5A

2.4.16 LAN (RJ-45) Port 2 (CN19)

Pin Name

Signal Type

Signal level

DIFF

LAN2_MDI0-

DIFF

ACT/LINK

LED

SPEED

LED

Summary of Contents for AAEON GENE-CML5

Page 1: ...Last Updated March 11 2021 GENE CML5 3 5 Subcompact Board User s Manual 2nd Ed ...

Page 2: ...d in this manual is intended to be accurate and reliable However the original manufacturer assumes no responsibility for its use or for any infringements upon the rights of third parties that may result from its use The material in this document is for product information only and is subject to change without notice While reasonable efforts have been made in the preparation of this document to ass...

Page 3: ...ademark of Microsoft Corp Intel Pentium and Celeron are registered trademarks of Intel Corporation Intel Core is a registered trademark of Intel Corporation ITE is a trademark of Integrated Technology Express Inc IBM PC AT PS 2 and VGA are trademarks of International Business Machines Corporation All other product names or trademarks are properties of their respective owners ...

Page 4: ...roduct please make sure the following items have been shipped Item Quantity GENE CML5 1 CPU Cooler TH1CML5010 1 CPU Cooler Backplate TH6CML5010 1 Screw Kit 9767ECD001 1 If any of these items are missing or damaged please contact your distributor or sales representative immediately ...

Page 5: ...d descriptions and explanations on the product s hardware and software features if any its specifications dimensions jumper connector settings definitions and driver installation instructions if any to facilitate users in setting up their product Users may refer to the product page at AAEON com for the latest version of this document ...

Page 6: ...transient over voltage 7 Always disconnect this device from any AC supply before cleaning 8 While cleaning use a damp cloth instead of liquid or spray detergents 9 Make sure the device is installed near a power outlet and is easily accessible 10 Keep this device away from humidity 11 Place the device on a solid surface during installation to prevent falls 12 Do not cover the openings on the device...

Page 7: ...usion to the device iii Exposure to moisture iv Device is not working as expected or in a manner as described in this manual v The device is dropped or damaged vi Any obvious signs of damage displayed on the device 18 DO NOT LEAVE THIS DEVICE IN AN UNCONTROLLED ENVIRONMENT WITH TEMPERATURES BEYOND THE DEVICE S PERMITTED STORAGE TEMPERATURES SEE CHAPTER 1 TO PREVENT DAMAGE ...

Page 8: ...plosion if the battery is incorrectly replaced Replace only with the same or equivalent type recommended by the manufacturer Dispose of used batteries according to the manufacturer s instructions and your local government s recycling or disposal directives Attention Il y a un risque d explosion si la batterie est remplacée de façon incorrecte Ne la remplacer qu avec le même modèle ou équivalent re...

Page 9: ...质或元素名称及含量 AAEON Main Board Daughter Board Backplane 部件名称有毒有害物质或元素铅 Pb 汞 Hg 镉 Cd 六价铬 Cr VI 多溴联苯 PBB 多溴二苯醚 PBDE 印刷电路板及其电子组件外部信号连接器及线材 O 表示该有毒有害物质在该部件所有均质材料中的含量均在 SJ T 11363 2006 标准规定的限量要求以下 X 表示该有毒有害物质至少在该部件的某一均质材料中的含量超出 SJ T 11363 2006 标准规定的限量要求备注此产品所标示之环保使用期限系指在一般正常使用状况下 ...

Page 10: ...henyl Ethers PBDE PCB Other Components O O O O O Wires Connectors for External Connections O O O O O O O The quantity of poisonous or hazardous substances or elements found in each of the component s parts is below the SJ T 11363 2006 stipulated requirement X The quantity of poisonous or hazardous substances or elements found in at least one of the component s parts is beyond the SJ T 11363 2006 s...

Page 11: ...isable Selection JP2 12 2 3 4 LVDS Backlight Control Selection JP3 12 2 3 5 Clear CMOS Jumper JP5 12 2 4 List of Connectors 13 2 4 1 COM Port 1 Port 2 CN1 CN2 14 2 4 2 External 5VSB Input CN3 16 2 4 3 External Power Input CN5 16 2 4 4 Audio I O Port CN6 17 2 4 5 Digital I O Port CN7 18 2 4 6 SATA Port CN8 CN9 19 2 4 7 5V Output for SATA HDD CN10 19 2 4 8 Battery Connector CN11 20 2 4 9 USB 2 0 Por...

Page 12: ...DIMM2 36 2 5 Block Diagram 37 Chapter 3 AMI BIOS Setup 38 3 1 System Test and Initialization 39 3 2 AMI BIOS Setup 40 3 3 Setup Submenu Main 41 3 4 Setup Submenu Advanced 42 3 4 1 Trusted Computing 43 3 4 2 CPU Configuration 45 3 4 3 SATA Configuration 47 3 4 4 Hardware Monitor 49 3 4 4 1 Smart Fan Mode Configuration 50 3 4 5 SIO Configuration 51 3 4 5 1 Serial Port 1 Configuration 52 3 4 5 2 Seri...

Page 13: ... 68 3 6 Setup Submenu Security 69 3 6 1 Secure Boot 70 3 6 1 1 Key Management 71 3 7 Setup Submenu Boot 73 3 7 1 BBS Priorities 74 3 8 Setup Submenu Save Exit 75 Chapter 4 Driver Installation 76 4 1 Driver Download Installation 77 Appendix A I O Information 79 A 1 I O Address Map 80 A 2 Memory Address Map 82 A 3 IRQ Mapping Chart 83 Appendix B Mating Connectors and Cables 86 B 1 Mating Connectors ...

Page 14: ...3 5 Subcompact Board GENE CML5 Chapter 1 Chapter 1 Product Specifications ...

Page 15: ...U Frequency Up to 4 4GHz Chipset Intel Q470E H420E Q470 Memory Type DDR4 2933 2666 2400 MHz SODIMM x 2 Dual Channel Non ECC Max Memory Capacity Up to 64GB BIOS AMI UEFI Wake on LAN Yes Watchdog Timer 255 Levels Power Requirement 12V Power Supply Type AT ATX Default AT Power Consumption Typical Intel Core i7 10700TE DDR4 3200Mhz 32GB 4 47A at 12V Dimension L x W 5 75 x 4 146mm x 101 7mm Operating T...

Page 16: ...se RJ45 x1 Intel i219 10 100 1000Base RJ45 x1 Support vPro only with i5 i7 Q470 Q470E variant Audio High Definition Audio Interface Line in Line out MIC Without Amplifier USB Port USB3 2 Gen 2 x 2 Rear I O Gen 2 for Q470 Q470E only USB2 0 x 4 Pin header Serial Port RS 232 422 485 x 2 Parallel Port HDD Interface FDD Interface SSD SATA III 6 0 Gbps x 2 SATA power connector x 1 5V Expansion Slot M 2 ...

Page 17: ...Chapter 1 Product Specifications 4 3 5 Subcompact Board GENE CML5 I O SIM TPM TPM 2 0 Touch Others ...

Page 18: ...3 5 Subcompact Board GENE CML5 Chapter 2 Chapter 2 Hardware Information ...

Page 19: ...Chapter 2 Hardware Information 6 3 5 Subcompact Board GENE CML5 2 1 Dimensions ...

Page 20: ...Chapter 2 Hardware Information 7 3 5 Subcompact Board GENE CML5 With Thermal Option Part No GENE CML5 FAN01 ...

Page 21: ...Chapter 2 Hardware Information 8 3 5 Subcompact Board GENE CML5 Thermal Option Assembly ...

Page 22: ...Chapter 2 Hardware Information 9 3 5 Subcompact Board GENE CML5 2 2 Jumpers and Connectors ...

Page 23: ...Chapter 2 Hardware Information 10 3 5 Subcompact Board GENE CML5 ...

Page 24: ... LVDS Operating VDD Selection Backlight VCC Selection JP2 Auto Power Button Enable Disable Selection JP3 LVDS Backlight BKLT Control Selection JP5 Clear CMOS 2 3 1 LVDS Operating VDD Selection JP1 3 3V Default 5V Note To avoid damage to the system do connect Pins 1 3 5 with Pins 2 4 6 2 3 2 LVDS Backlight VCC Selection JP1 12V 5V Default Note To avoid damage to the system do connect Pins 1 3 5 wit...

Page 25: ...utton Enable Disable Selection JP2 Disabled Enabled Default Note When disabled Power Button must be used to power on the system 2 3 4 LVDS Backlight Control Selection JP3 VR Mode PWM Mode Default 2 3 5 Clear CMOS Jumper JP5 Normal Default Clear CMOS 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 ...

Page 26: ...rt 1 CN3 External 5VSB Input CN5 External Power Input CN6 Audio I O Port CN7 Digital IO Port CN8 SATA Port CN9 SATA Port CN10 5V Output for SATA HDD CN11 Battery Connector CN12 USB 2 0 Port CN13 USB 2 0 Port CN14 FPC CN15 FAN CONN CN16 Front Panel header CN17 LVDS Port CN18 LVDS Port Inverter Backlight Connector CN19 LAN RJ 45 Port 2 CN20 LAN RJ 45 Port 1 CN21 USB3 2 Gen2 Port 1 Port 2 Dual Port C...

Page 27: ...bug Port CN26 M 2 M Key DIMM1 DDR4 SO DIMM Slot DIMM2 DDR4 SO DIMM Slot 2 4 1 COM Port 1 Port 2 CN1 CN2 Note CN1 is COM Port 2 and CN2 is COM Port 1 RS 232 Pin Pin Name Signal Type Signal Level 1 DCD IN 2 DSR IN 3 RX IN 4 RTS OUT 5 TX OUT 6 CTS IN 7 DTR OUT 8 RI IN 9 GND GND 1 2 3 4 5 6 7 8 9 ...

Page 28: ...al Type Signal Level 1 RS485_ D I O 2 NC 3 RS485_D I O 4 NC 5 NC 6 NC 7 NC 8 NC 9 GND GND RS 422 Pin Pin Name Signal Type Signal Level 1 RS422_TX OUT 2 NC 3 RS422_TX OUT 4 NC 5 RS422_RX IN 6 NC 7 RS422_RX IN 8 NC 9 GND GND Note 1 COM Port RS 232 422 485 can be set by BIOS Default is RS 232 ...

Page 29: ...bcompact Board GENE CML5 2 4 2 External 5VSB Input CN3 Pin Pin Name Signal Type Signal Level 1 PS_ON OUT 5V 2 GND GND 3 V5A_SB_IN PWR 5V 2 4 3 External Power Input CN5 Pin Pin Name Signal Type Signal Level 1 VIN_EXT PWR 12V 2 GND GND 12V GND ...

Page 30: ...ort CN6 Pin Pin Name Signal Type Signal Level 1 MIC_L IN 2 MIC_R IN 3 GND_AUDIO GND 4 LINE_L IN 5 LINE_R IN 6 GND_AUDIO GND 7 LEFT_OUT OUT 8 GND_AUDIO GND 9 RIGHT_OUT OUT 10 5V_AUDIO PWR 5V MIC_L 1 10 MIC_R LINE_L_IN LINE_R_IN LEFT_OUT RIGHT_OUT 5V_AUDIO GND_AUDIO GND_AUDIO GND_AUDIO ...

Page 31: ...bcompact Board GENE CML5 2 4 5 Digital I O Port CN7 Pin Pin Name Signal Type Signal Level 1 V5S PWR 5V 2 DIO0 I O 3 DIO1 I O 4 DIO2 I O 5 DIO3 I O 6 DIO4 I O 7 DIO5 I O 8 DIO6 I O 9 DIO7 I O 10 GND GND Note DIO V5S max driving current is 0 5A ...

Page 32: ...9 Pin Pin Name Signal Type Signal Level 1 GND GND 2 SATA_TX DIFF 3 SATA_TX DIFF 4 GND GND 5 SATA_RX DIFF 6 SATA_RX DIFF 7 GND GND 2 4 7 5V Output for SATA HDD CN10 Pin Pin Name Signal Type Signal Level 1 5V PWR 5V 2 GND GND Note SATA HDD V5S max driving current is 0 5A Pin 1 Pin 7 5V GND ...

Page 33: ...tery Connector CN11 Pin Pin Name Signal Type Signal level 1 3 3V PWR 3 3V 2 GND GND 2 4 9 USB 2 0 Port CN12 Pin Pin Name Signal Type Signal Level 1 V5A_USB_3 PWR 5V 2 V5A_USB_3 PWR 5V 3 USBD5 DIFF 4 USBD6 DIFF 5 USBD5 DIFF 6 USBD6 DIFF 7 GND GND 8 GND GND 9 GND GND 10 GND GND ...

Page 34: ...on 21 3 5 Subcompact Board GENE CML5 2 4 10 USB 2 0 Port CN13 Pin Pin Name Signal Type Signal Level 1 V5A_USB_2 PWR 5V 2 V5A_USB_2 PWR 5V 3 USBD3 DIFF 4 USBD4 DIFF 5 USBD3 DIFF 6 USBD4 DIFF 7 GND GND 8 GND GND 9 GND GND 10 GND GND ...

Page 35: ...nal Type Signal Level 1 V3P3S PWR 3 3V 2 V3P3S PWR 3 3V 3 V3P3S PWR 3 3V 4 SMB_DATA I O 5 SMB_CLK I O 6 BUF_PLT_RST I O 7 V3P3A PWR 3 3V 8 GND GND 9 PCIE_18_RXP DIFF 10 PCIE_18_RXN DIFF 11 GND GND 12 PCIE_20_RXP DIFF 13 PCIE_20_RXN DIFF 14 GND GND 15 PCIE_19_RXP DIFF 16 PCIE_19_RXN DIFF 17 GND GND ...

Page 36: ...N DIFF 20 GND GND 21 PCIE_20_TXN DIFF 22 PCIE_20_TXP DIFF 23 GND GND 24 PCIE_19_TXN DIFF 25 PCIE_19_TXP DIFF 26 GND GND 27 PCIE_18_TXN DIFF 28 PCIE_18_TXP DIFF 29 GND GND 30 CLK_PCIE_FPC_N DIFF 31 CLK_PCIE_FPC_P DIFF 32 GND GND 33 PCIE_17_TXN DIFF 34 PCIE_17_TXP DIFF 35 GND GND 36 V12S PWR 37 V12S PWR 38 V12S PWR 39 V12S PWR 40 V12S PWR ...

Page 37: ... CPU Fan CN15 Pin Pin Name Signal Type Signal Level 1 GND GND 2 FAN_POWER PWR 12V 3 FAN_TAC OUT 4 FAN_CTL IN Note FAN Connector FAN_POWER max driving current is 1A 2 4 13 Digital I O Port CN16 Pin Pin Name Signal Type Signal Level 1 GND GND 2 EXT_PWRBTN I O 3 FP_HDLED I O ...

Page 38: ... 6 V5S PWR 7 GND GND 8 PWRLED I O 9 GND GND 10 HWRST I O 2 4 14 LVDS Port CN17 Note LVDS Operating VDD can be set by JP1 reference Ch 2 3 1 for details Pin Pin Name Signal Type Signal Level 1 LVDS_BKLTEN I O 3 VDD_LVDS PWR 5 LVDSA_CLK DIFF 7 VDD_LVDS PWR 9 LVDSA_DATA0 DIFF 11 LVDSA_DATA1 DIFF 13 LVDSA_DATA2 DIFF 15 LVDSA_DATA3 DIFF ...

Page 39: ... DIFF 25 LVDSB_DATA3 DIFF 27 VDD_LVDS PWR 29 LVDSB_CLK DIFF 2 LVDS_BKLCTL I O 4 GND GND 6 LVDSA_CLK DIFF 8 GND GND 10 LVDSA_DATA0 DIFF 12 LVDSA_DATA1 DIFF 14 LVDSA_DATA2 DIFF 16 LVDSA_DATA3 DIFF 18 LVDS_DDC_CLK I O 20 LVDSB_DATA0 DIFF 22 LVDSB_DATA1 DIFF 24 LVDSB_DATA2 DIFF 26 LVDSB_DATA3 DIFF 28 GND GND 30 LVDSB_CLK DIFF Note LVDS Connector VDD_LVDS max driving current is 0 5A ...

Page 40: ...BKLT PWR 2 VCC_LVDS_BKLT PWR 3 L_BKLTNESS I O 4 GND GND 5 GND GND 6 LVDS_BKLTEN I O Note 1 LVDS Backlight VCC can be by JP1 See Ch 2 3 2 Note 2 Backlight Connector VCC_LVDS_BKLT max driving current is 1 5A 2 4 16 LAN RJ 45 Port 2 CN19 Pin Pin Name Signal Type Signal level 1 LAN2_MDI0 DIFF 2 LAN2_MDI0 DIFF 3 LAN2_MDI1 DIFF 4 LAN2_MDI2 DIFF 1 ACT LINK LED SPEED LED 8 ...

Page 41: ...vel 5 LAN2_MDI2 DIFF 6 LAN2_MDI1 DIFF 7 LAN2_MDI3 DIFF 8 LAN2_MDI3 DIFF 2 4 17 LAN RJ 45 Port 2 CN20 Pin Pin Name Signal Type Signal level 1 LAN1_MDI0 DIFF 2 LAN1_MDI0 DIFF 3 LAN1_MDI1 DIFF 4 LAN1_MDI2 DIFF 5 LAN1_MDI2 DIFF 6 LAN1_MDI1 DIFF 7 LAN1_MDI3 DIFF 8 LAN1_MDI3 DIFF 1 ACT LINK LED SPEED LED 8 ...

Page 42: ...l Type Signal Level 1 V5A_USB_1 PWR 5V 2 USBD2 DIFF 3 USBD2 DIFF 4 GND GND 5 USB3_RX2_CON_N DIFF 6 USB3_RX2_CON_P DIFF 7 GND GND 8 USB3_TX2_CON_N DIFF 9 USB3_TX2_CON_P DIFF 10 V5A_USB_0 PWR 5V 11 USBD1 DIFF 12 USBD1 DIFF 13 GND GND 14 USB3_RX1_CON_N DIFF 15 USB3_RX1_CON_P DIFF 16 GND GND 17 USB3_TX1_CON_N DIFF 18 USB3_TX1_CON_P DIFF ...

Page 43: ...P DIFF 2 GND GND 3 DDI1_TX0_DN DIFF 4 DDI1_TX1_DP DIFF 5 GND GND 6 DDI1_TX1_DN DIFF 7 DDI1_TX2_DP DIFF 8 GND GND 9 DDI1_TX2_DN DIFF 10 DDI1_TX3_DP DIFF 11 GND GND 12 DDI1_TX3_DN DIFF 13 DDI1_AUX_EN IO 14 GND GND 15 DDI1_DP_CTRLCLK_AUX_DP DIFF 16 GND GND 17 DDI1_DP_CTRLDATA_AUX_DN DIFF 18 DDI1_DP_HPD DDI1_DP_HPD 19 GND GND 20 V3P3S PWR ...

Page 44: ...in Name Signal Type Signal Level 1 VGA_RED_CON OUT 2 VGA_GREEN_CON OUT 3 VGA_BLUE_CON OUT 4 NC 5 GND GND 6 RED_GND_RTN GND 7 GREEN_GND_RTN GND 8 BLUE_GND_RTN GND 9 5V PWR 5V 10 NC 11 NC 12 VGA_DDCDAT_CON I O 5V 13 VGA_HSYNC_CON OUT 14 VGA_VSYNC_CON OUT 15 VGA_DDCCLK_CON I O 5V 1 6 10 11 15 5 ...

Page 45: ...d GENE CML5 2 4 21 LPC Port CN24 Pin Pin Name Signal Type Signal Level 1 LPC_AD0 I O 2 LPC_AD1 I O 3 LPC_AD2 I O 4 LPC_AD3 I O 5 V3P3S PWR 3 3V 6 LPC_FRAME IN 7 BUF_PLT_RST OUT 8 GND GND 9 CLK_LPCC_25M OUT 10 I2C0_SDA I O 11 I2C0_SCL OUT 12 INT_SERIRQ GND ...

Page 46: ... Level 1 SPI_SO_F OUT 2 GND GND 3 SPI_CLK_F IN 4 V3P3A_SPI PWR 3 3V 5 SPI_SI_F IN 6 SPI_CE0 _F IN 7 NC 2 4 23 M 2 M Key 2280 CN26 Pin Pin Name Signal Type Signal Level 1 GND GND 2 V3P3S PWR 3 3V 3 GND GND 4 V3P3S PWR 3 3V 5 PCIE_8_RXN DIFF 6 CARD_PWR_OFF_R IN 7 PCIE_8_RXP DIFF P IN 1 P IN 2 P IN 3 P IN 4 P IN 5 P IN 6 P IN 7 ...

Page 47: ...D OUT 11 PCIE_8_TXN_C DIFF 12 V3P3S PWR 3 3V 13 PCIE_8_TXP_C DIFF 14 V3P3S PWR 3 3V 15 GND GND 16 V3P3S PWR 3 3V 17 PCIE_7_RXN DIFF 18 V3P3S PWR 3 3V 19 PCIE_7_RXP DIFF 20 N C 21 GND GND 22 N C 23 PCIE_7_TXN_C DIFF 24 N C 25 PCIE_7_TXP_C GND 26 N C 27 GND GND 28 N C 29 PCIE_6_RXN DIFF 30 N C 31 PCIE_6_RXP DIFF 32 N C 33 GND GND ...

Page 48: ...IFF 36 N C 37 PCIE_6_TXP_C DIFF 38 SATA_DEVSLP0 IN 39 GND GND 40 SMB_CLK_KMB IN 41 M2M_A_RXP DIFF 42 N C 43 M2M_A_RXN DIFF 44 N C 45 GND GND 46 N C 47 M2M_A_TXN_C DIFF 48 N C 49 M2M_A_TXP_C DIFF 50 BUF_PLT_RST IN 51 GND GND 52 M2M_CLKREQ IN 53 CLK_PCIE_M2M_N_R 54 PCIE_WAKE IN 55 CLK_PCIE_M2M_P_R 56 N C 57 GND GND 58 N C 67 N C ...

Page 49: ...compact Board GENE CML5 Pin Pin Name Signal Type Signal Level 68 SUS_CLK_M2M IN 69 PEDET_R OUT 70 V3P3S PWR 3 3V 71 GND GND 72 V3P3S PWR 3 3V 73 GND GND 74 V3P3S PWR 3 3V 75 GND GND 2 4 24 DDR4 SO DIMM Slot DIMM1 DIMM2 Standard Specifications ...

Page 50: ...Chapter 2 Hardware Information 37 3 5 Subcompact Board GENE CML5 2 5 Block Diagram ...

Page 51: ...3 5 Subcompact Board GENE CML5 Chapter 3 Chapter 3 AMI BIOS Setup ...

Page 52: ...ration against the values stored in the CMOS memory and BIOS NVRAM If a system configuration is not found or an error is detected the module will load the default configuration and reboot automatically There are four situations in which you will need to setup system configuration 1 You are starting your system for the first time 2 You have changed the hardware attached to your system 3 The system ...

Page 53: ...when the power is turned off To enter BIOS Setup press Del or ESC immediately while your computer is powering up The function for each interface can be found below Main Date and time can be set here Press Tab to switch between date elements Advanced Access hardware monitor and advanced board features options Chipset Host bridge parameters Security The setup administrator password can be set here B...

Page 54: ...Chapter 3 AMI BIOS Setup 41 3 5 Subcompact Board GENE CML5 3 3 Setup Submenu Main ...

Page 55: ...Chapter 3 AMI BIOS Setup 42 3 5 Subcompact Board GENE CML5 3 4 Setup Submenu Advanced ...

Page 56: ...ol and INT1A interface will not be available SHA 1 PCR Bank Disabled Optimal Default Failsafe Default Enabled Enable or Disable SHA 1 PCR Bank SHA256 PCR Bank Disabled Enabled Optimal Default Failsafe Default Enable or Disable SHA256 PCR Bank Pending Operation None Optimal Default Failsafe Default TPM Clear Schedule an Operation for the Security Device NOTE Your Computer will reboot during restart...

Page 57: ...TCG_2 Optimal Default Failsafe Default Select the TCG2 Spec Version Support TCG_1_2 Compatible mode for Win8 Win10 TCG_2 Support new TCG2 protocol and event format for Win10 or later Physical Presence Spec Version 1 2 1 3 Optimal Default Failsafe Default Select to Tell O S to support PPI Spec Version 1 2 or 1 3 Note some HCK tests might not support 1 3 Device Select TPM 1 2 TPM 2 0 Auto Optimal De...

Page 58: ...nable in each processor package Intel VMX Virtualization Technology Disabled Enabled Optimal Default Failsafe Default When enabled a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology C States Disabled Enabled Optimal Default Failsafe Default Enable Disable CPU Power Management Allows CPU to go to C states when it s not 100 utilized Intel R SpeedStep tm Disabled...

Page 59: ...up 46 3 5 Subcompact Board GENE CML5 Options Summary Turbo Mode Disabled Enabled Optimal Default Failsafe Default Enable Disable processor Turbo Mode requires Intel Speed Step or Intel Speed Shift to be available and enabled ...

Page 60: ...ble SATA Device SATA Mode Selection AHCI Optimal Default Failsafe Default Intel RST Premium With Intel Optane System Acceleration Determines how SATA controller s operate M 2 CN26 Disabled Enabled Optimal Default Failsafe Default Enable or Disable SATA Port Port 2 Disabled Enabled Optimal Default Failsafe Default Enable or Disable SATA Port Table Continues on Next Page ...

Page 61: ...ot Plug Disabled Optimal Default Failsafe Default Enabled Designates this port as Hot Pluggable Port 3 Disabled Enabled Optimal Default Failsafe Default Enable or Disable SATA Port Hot Plug Disabled Optimal Default Failsafe Default Enabled Designates this port as Hot Pluggable ...

Page 62: ...Chapter 3 AMI BIOS Setup 49 3 5 Subcompact Board GENE CML5 3 4 4 Hardware Monitor Options Summary Smart Fan Disabled Enabled Optimal Default Failsafe Default Enables or Disables Smart Fan ...

Page 63: ...lsafe Default Fan 1 Smart Fan Control Manual Duty Mode Auto Duty Cycle Mode Optimal Default Failsafe Default Smart Fan Mode Select Temperature Source CPU PECI Temperature System Temperature Optimal Default Failsafe Default System Temperature 2 Select the monitored temperature source for this fan Temperature 1 60 Duty Cycle 1 85 Auto fan speed control Fan speed will follow different temperature by ...

Page 64: ...Chapter 3 AMI BIOS Setup 51 3 5 Subcompact Board GENE CML5 3 4 5 SIO Configuration ...

Page 65: ...se This Device Disable Enable Optimal Default Failsafe Default Enable or Disable this Logical Device Possible Use Automatic Settings Optimal Default Failsafe Default IO 3F8h IRQ 4 IO 2F8h IRQ 3 Allows user to change Device s Resource settings New settings will be reflected on This Setup Page after System restarts ...

Page 66: ...lt Failsafe Default Enable or Disable this Logical Device Possible Use Automatic Settings Optimal Default Failsafe Default IO 2F8h IRQ 3 IO 3F8h IRQ 4 Allows user to change Device s Resource settings New settings will be reflected on This Setup Page after System restarts Mode RS232 Optimal Default Failsafe Default RS422 RS485 UART RS232 422 485 selection ...

Page 67: ...AMT Configuration Options Summary AMT BIOS Features Disable Enable Optimal Default Failsafe Default When disabled AMT BIOS Features are no longer supported and user is no longer able to access MEBx Setup Note This option does not disable Manageability Features in FW ...

Page 68: ...4 7 Firmware Update Configuration Options Summary Me FW Image Re Flash Disabled Optimal Default Failsafe Default Enabled Enable Disable Me FW Image Re Flash function FW Update Disabled Enabled Optimal Default Failsafe Default Enable Disable ME FW Update function ...

Page 69: ...Serial Port Console Redirection Options Summary Console Redirection Disabled Optimal Default Failsafe Default Enabled Console Redirection Enable or Disable Console Redirection EMS Disabled Optimal Default Failsafe Default Enabled Console Redirection Enable or Disable ...

Page 70: ...SCII char set VT100 Extends VT100 to support color function keys etc VT UTF8 Uses UTF8 encoding to map Unicode chars onto 1 or more bytes Bits Per second 9600 19200 38400 57600 115200 Optimal Default Failsafe Default Selects serial port transmission speed The speed must be matched on the other side Long or noisy lines may require lower speeds Data Bits 7 8 Optimal Default Failsafe Default Parity N...

Page 71: ...t Flow Control None Optimal Default Failsafe Default Hardware RTS CTS Flow control can prevent data loss from buffer overflow When sending data if the receiving buffers are full a stop signal can be sent to stop the data flow Once the buffers are empty a start signal can be sent to re start the flow Hardware flow control uses two wires to send start stop signals VT UTF8 Combo Key Support Disabled ...

Page 72: ...n 80x24 Optimal Default Failsafe Default 80x25 On Legacy OS the Number of Rows and Columns supported redirection Redirect After POST Always Enable Optimal Default Failsafe Default BootLoader When Bootloader is selected then Legacy Console Redirection is disabled before booting to legacy OS When Always Enable is selected then Legacy Console Redirection is enabled for legacy OS Default setting for t...

Page 73: ...lt ANSI VT UTF8 is the preferred terminal type for out of band management The next best choice is VT100 and then VT100 See above in Console Redirection Settings page for more Help with Terminal Type Emulation Bits Per second EMS 9600 19200 57600 115200 Optimal Default Failsafe Default Flow Control EMS None Optimal Default Failsafe Default Hardware RTS CTS Software xon xoff Continued on Next Page ...

Page 74: ...rol can prevent data loss from buffer overflow When sending data if the receiving buffers are full a stop signal can be sent to stop the data flow Once the buffers are empty a start signal can be sent to re start the flow Hardware flow control uses two wires to send start stop signals ...

Page 75: ...ower mode State After G3 Always On Always Off Last State Optimal Default Failsafe Default Specify what state to go to when power is re applied after a power failure G3 state RTC wake system from S5 Disable Optimal Default Failsafe Default Fixed Time Fixed Time System will wake on the hr min sec specified n Dynamic Time System will wake on the current time Increase minute s ...

Page 76: ... 3 5 Subcompact Board GENE CML5 3 4 10 Digital IO Port Configuration Options Summary DIO Port Output Input Set DIO as Input or Output Output Level High Optimal Default Failsafe Default Low Set output level when DIO pin is output ...

Page 77: ...Chapter 3 AMI BIOS Setup 64 3 5 Subcompact Board GENE CML5 3 5 Setup Submenu Chipset ...

Page 78: ...Chapter 3 AMI BIOS Setup 65 3 5 Subcompact Board GENE CML5 3 5 1 North Bridge ...

Page 79: ... Panel Type 640x480 18bit 60Hz 800x480 18bit 60Hz 800x600 18bit 60Hz 1024x600 18bit 60Hz 1024x768 18bit 60Hz 1024x768 24bit 60Hz Optimal Default Failsafe Default 1280x768 24bit 60Hz 1280x1024 48bit 60Hz 1366x768 24bit 60Hz 1440x900 48bit 60Hz 1600x1200 48bit 60Hz 1920x1080 48bit 60Hz 1920x1200 48bit 60Hz Select LCD panel used by Internal Graphics Device by selecting the appropriate setup item ...

Page 80: ...type Backlight Type Normal Optimal Default Failsafe Default Inverted Select backlight control signal type Backlight Level 0 10 20 30 40 50 60 70 80 Optimal Default Failsafe Default 90 100 Select backlight control level Backlight PWM Freq 100Hz 200Hz 220Hz Optimal Default Failsafe Default 500Hz 1KHz 2 2KHz 6 5KHz Select PWM frequency of backlight control signal ...

Page 81: ... Summary HD Audio Disabled Enabled Optimal Default Failsafe Default Control Detection of the HD Audio device Disabled HDA will be unconditionally disabled Enabled HDA will be unconditionally enabled PCH Lan Controller Disabled Enabled Optimal Default Failsafe Default Enable Disable onboard NIC ...

Page 82: ...hen the user enters the Setup utility A User Password does not provide access to many of the features in the Setup utility Select the password you wish to set and press Enter In the dialog box enter your password must be between 3 and 20 letters or numbers Press Enter and retype your password to confirm Press Enter again to set the password Removing the Password Select the password you want to rem...

Page 83: ...em is in User mode The mode change requires platform reset Secure Boot Mode Custom Optimal Default Failsafe Default Standard Secure Boot mode options Standard or Custom In Custom mode Secure Boot Policy variables can be configured by a physically present user without full authentication Restore Factory Keys Force System to User Mode Install factory default Secure Boot key databases Reset To Setup ...

Page 84: ...de change requires platform reset Restore Factory Keys Force System to User Mode Install factory default Secure Boot key databases Reset To Setup Mode Delete all Secure Boot key databases from NVRAM Export Secure Boot variables Copy NVRAM content of Secure Boot variables to files in a root folder on a file system device Enroll Efi Image Allow the image to run in Secure Boot mode Enroll SHA256 Hash...

Page 85: ... Delete Key Exchange Keys Details Export Update Append Delete Authorized Signatures Details Export Update Append Delete Forbidden Signatures Details Export Update Append Delete Authorized TimeStamps Update Append OsRecovery Signatures Update Append Enroll Factory Defaults or load certificates from a file 1 Public Key Certificate a EFI_SIGNATURE_LIST b EFI_CERT_X509 DER c EFI_CERT_RSA2048 bin d EFI...

Page 86: ...GENE CML5 3 7 Setup Submenu Boot Options Summary Quiet Boot Disabled Enabled Optimal Default Failsafe Default Enable or Disable showing boot logo LAN UEFI Pxe Driver Disabled Optimal Default Failsafe Default Enabled Enabled Disable LAN UEFI PXE Driver ...

Page 87: ...Chapter 3 AMI BIOS Setup 74 3 5 Subcompact Board GENE CML5 3 7 1 BBS Priorities ...

Page 88: ...Chapter 3 AMI BIOS Setup 75 3 5 Subcompact Board GENE CML5 3 8 Setup Submenu Save Exit ...

Page 89: ...3 5 Subcompact Board GENE CML5 Chapter 4 Chapter 4 Driver Installation ...

Page 90: ...ll them Step 1 Install Chipset Drivers 1 Open the Step 1 Chipset folder 2 Run the SetupChipset exe in the folder 3 Follow the instructions 4 Drivers will be installed automatically Step 2 Install Graphics Drivers 1 Open the Step 2 Graphic folder 2 Run the igxpin exe file in the folder 3 Follow the instructions 4 Drivers will be installed automatically Step 3 Install Network Driver 1 Open the Step ...

Page 91: ...s 4 Drivers will be installed automatically Step 5 Install Serial IO Drivers 1 Open the Step 5 SerialIO folder 2 Run the SetupSerialIO exe file in the folder 3 Follow the instructions 4 Drivers will be installed automatically Step 6 Install ME Drivers 1 Click on the Step 6 ME folder 2 Run the SetupME exe file in the folder 3 Follow the instructions 4 Drivers will be installed automatically ...

Page 92: ...3 5 Subcompact Board GENE CML5 Appendix A Appendix A I O Information ...

Page 93: ...Appendix A I O Information 80 3 5 Subcompact Board GENE CML5 A 1 I O Address Map ...

Page 94: ...Appendix A I O Information 81 3 5 Subcompact Board GENE CML5 ...

Page 95: ...Appendix A I O Information 82 3 5 Subcompact Board GENE CML5 A 2 Memory Address Map ...

Page 96: ...Appendix A I O Information 83 3 5 Subcompact Board GENE CML5 A 3 IRQ Mapping Chart ...

Page 97: ...Appendix A I O Information 84 3 5 Subcompact Board GENE CML5 ...

Page 98: ...Appendix A I O Information 85 3 5 Subcompact Board GENE CML5 ...

Page 99: ...3 5 Subcompact Board GENE CML5 Appendix B Appendix B Mating Connectors and Cables ...

Page 100: ...0TW 01 Audio Cable 1709100254 CN8 SATA Connector TechBest 007 01 00757 SATA Cable 1709070460 CN9 SATA Connector TechBest 007 01 00757 SATA Cable 1709070460 CN10 SATA Power Connector PINREX 721 81 02TW 00 SATA Power Cable 1702150155 CN12 USB2 0 Connector Aces 50238 01041 003 USB2 0 Cable 170010010D CN13 USB2 0 Connector Aces 50238 01041 003 USB2 0 Cable 170010010D CN14 FPC Connector Panasoni c AYF5...

Page 101: ...3 5 Subcompact Board GENE CML5 Appendix C Appendix C Digital I O Ports ...

Page 102: ...Appendix C Digital I O Ports 89 3 5 Subcompact Board GENE CML5 C 1 Digital I O Register ...

Page 103: ...Appendix C Digital I O Ports 90 3 5 Subcompact Board GENE CML5 ...

Page 104: ... out 2 low 2 high Outportb 0x2E 0x87 enter configuration Outportb 0x2E 0x87 Outportb 0x2E 0x07 set LDN Outportb 0x2F 0x06 Outportb 0x2E 0x88 GPIO set 8x Output enable register Outportb 0x2F 0xF0 Outportb 0x2E 0x89 GPIO 8x output data register Outportb 0x2F 0x30 Outportb 0x2E 0xAA exit configuration ...

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