Astronics OMNIBUS II NI PXIe, User Manual

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OmniBus II PCIe/PXIe User Manual B-1
APPENDIX B: SPECIFICATIONS
B.1 General
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2 Core I/O sites
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8 bidirectional TTL discrete I/O per core
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2 user controlled LED indicators per core
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64 MB memory per core (ECC)
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RoHS
B.2 Interfaces (Model Dependent)
MIL-STD-1553
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Up to 2 dual-redundant channels per core
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BC/RT/MON (single or multi-function)
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Hardware controlled transmit scheduling
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CH/TA/SA message filtering
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Sequential monitor and time stamping
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Error injection including MBZC shifting
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Playback with errors
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Amplitude controls
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16 Open/GND avionics discrete I/O
ARINC 429 (Standard Module)
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Up to 8 Tx/8 Rx configurable channels per core
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Periodic and asynchronous messages
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Hardware controlled transmit schedule
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Hardware playback mode
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Sequential monitor and time stamping
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Programmable bit rate frequency
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Error detection and injection
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Parity bit inversion
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+/- bit count (8-33 bits)
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Intermessage gap error