Astronics OMNIBUS II NI PXIe, User Manual

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INTRODUCTION
1-2 OmniBus II NI PXIe User Manual
its own circuitry to handle the channels and protocols associated with it. The high
channel count and mixed protocol capabilities can be fully utilized without the risk
of overloading the host computer’s processor. IRIG and special timing circuits
allows channels, boards, and computers to be synchronized in time to each other
and to external devices.
OmniBus II is a newer, enhanced generation of the original OmniBus architecture.
Though there are similarities, the components of the two generations are not
interchangeable. Figure 1.2 illustrates the modular architecture of the OB2 PXIe
board.
Figure 1.2—The Two-Core Architecture of OmniBus II PXIe Card
SDRAM
PCIe
Connector
1:2 PCIe Switch
Protocol
Module
B
Core A
FPGA
Core B
FPGA
Flash
SDRAM
Flash
Protocol
Module
A
P1 P2
Avionics
Databuses
Avionics
Databuses
1 Lane PCIe