ASTRO VG-870B, Instruction Manual

Page: 179 / 579

Chapter 4
INTERFACE SETTINGS
161
Setting (5) [Dual (16 bits)], [Normal], configuration [8 + 8 bits]
With channels 1 and 3 forming one set and channels 2 and 4 forming another set, odd-numbered fields are output
using one set and even-numbered fields are output using the other set.
The 8 upper bits are output to channels 1 and 2, and the 8 lower bits are output to channels 3 and 4.
The example is that the resolution is 1280 × 1024, the dot clock frequency is 108 MHz with 16 bits level, 8 bits are
output to channel 1 and 8 bits are output to channel 2.
D 0 D 2 D 4 D 6
・・・
・・・
D 1272 D 1274 D 1276 D 1278
CLK
54MHz
1CH
2CH
3CH
4CH
D 1 D 3 D 5 D 7
・・・
D 1273 D 1275 D 1277 D 1279
・・・
D 1272 D 1274 D 1276 D 1278 D 0 D 2 D 4 D 6
D 1273 D 1275 D 1277 D 1279
・・・
D 1 D 3 D 5 D 7
[7：0] [7：0] [7：0] [7：0] [7：0] [7：0] [7：0] [7：0]
[15：8] [15：8] [15：8] [15：8] [15：8] [15：8] [15：8] [15：8]
[15：8] [15：8] [15：8] [15：8] [15：8] [15：8] [15：8] [15：8]
[7：0] [7：0] [7：0] [7：0] [7：0] [7：0] [7：0] [7：0]
Upper Bit [15:8] Lower Bit [7:0]
Upper Bit [15:8]
Lower Bit [7:0] Upper Bit [15:8] Lower Bit [7:0]
1CH 2CH 3CH 4CH