ASAHI KASEI
[AK4589]
MS0339-E-00
2004/09
-
37
-
Reset Function
When RSTN1 bit = “0”, ADC and DACs are powered-down but the internal register are not initialized. The analog
outputs go to VCOM voltage, DZF1-2 pins go to “H” and SDTO1 pin goes to “L”. Because some click noise occurs,
the analog output should muted externally if the click noise influences system application. Table 15 shows the power-up
sequence.
ADC Internal
State
RSTN1 bit
Normal Operation
Digital Block Power-down
Normal Operation
Don’t care
GD
GD
Clock In
MCLK,LRCK1,
BICK1
ADC In
(Analog)
“0”data
ADC Out
(Digital)
Normal Operation
Normal Operation
DAC Internal
State
“0”data
DAC In
(Digital)
DAC Out
(Analog)
GD
GD
(2)
(2)
(3)
(4)
(6)
(6)
DZF1/DZF2
(7)
Internal
RSTN1 bit
Digital Block Power-down
1~2/fs (9)
4~5/fs (9)
4
∼
5/fs (8)
(5)
516/fs
Init Cycle
(1)
Notes:
(1) The analog part of ADC is initialized after exiting the reset state.
(2) Digital output corresponding to analog input and analog output corresponding to digital input have the group
delay (GD).
(3) ADC output is “0” data at the power-down state.
(4) Click noise occurs when the internal RSTN bit becomes “1”. Please mute the digital output externally if the click
noise influences system application.
(5) When RSTN1 bit = “0”, the analog outputs go to VCOM voltage.
(6) Click noise occurs at 4
∼
5/fs after RSTN1 bit becomes “0”, and occurs at 1
∼
2/fs after RSTN1 bit becomes “1”.
This noise is output even if “0” data is input.
(7) The external clocks (MCLK, BICK1 and LRCK1) can be stopped in the reset mode. When exiting the reset
mode, “1” should be written to RSTN1 bit after the external clocks (MCLK, BICK1 and LRCK1) are fed.
(8) DZF pins go to “H” when the RSTN1 bit becomes “0”, and go to “L” at 6~7/fs after RSTN1 bit becomes “1”.
(9) There is a delay, 4~5/fs from RSTN1 bit “0” to the internal RSTN bit “0”.
Figure 15. Reset sequence example