54
3
VMIVME-3126A High Resolution, Isolated Analog-to-Digital Converter Board
Board Control Register Bit Definitions (Continued)
Bit 03:
SYS Reconfig -
The user sets this bit to a logical one (1) whenever
a change in channel configuration is desired (i.e., gain,
frequency). The channel or channels reconfigured are entered
into the Select Channel Register (SCR) prior to setting this bit.
The DSP periodically polls this bit to determine if the
configuration has changed. Sensing a change, the DSP reads the
SCR and begins processing the new configurations. While the
channel is being reconfigured, VMEbus activity should be
limited to reading the BRR for an indication on when normal
accesses can take place. The
SYS Reconfig
bit is reset after the
channel has been reconfigured.
Bit 02:
Chan Cal’d -
This is a status bit set by the DSP after the data for
the present calibration voltage is stored. This informs the user
that additional calibration voltage can be entered. The bit is reset
by the DSP after each
INIT CAL
or
CAL Done
operation.
Bit 01:
INIT CAL
- This bit is set to a logical one (1) by the user to initiate
calibration. Also, this bit is set for each voltage entered for
calibration. The bit is reset automatically by the calibration
routine.
Bit 00:
CAL Done -
The user sets this bit to a logical one (1) upon
completion of calibration. The DSP reads this bit to determine
when the user is finished and proceeds calculating the gain and
offset coefficients. The bit is reset to logical zero (0) after the DSP
finishes its calculations.
Table 3-6 User Gain Coefficients MSW and LSW
Address
Word
Channel
$XXC0
MSW
0
$XXC2
LSW
0
$XXC4
MSW
1
$XXC6
LSW
1
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