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Functional Description
ATCA-F125 (6873M Artwork) Installation and Use (6806800J94K
)
68
The SPD-SROM (Serial Presents Detect) on each DIMM module provides all necessary
information (speed, size, type and the like) to the boot firmware. The SPD-SROM is read
through I2C Bus connected to the P2020 QorIQ Integrated Processor.
4.3.4
Persistent Memory
On the ATCA-F125, the persistent memory is part of the DDR memory subsystem. A dedicated
register is available in the FPGA to enable or disable persistent memory by software. If
persistent memory is enabled, the memory contents of the main memory stays unchanged
after any applied reset, except power-up reset. After power-up reset the persistent memory
feature is disabled.
A special procedure needs to be followed to use the persistent memory feature. This procedure
is automatically executed by the U-Boot during initialization.
1. Set DDR_SDRAM_CFG_2[SR_IE] bit inside the memory controller of the P2020 QorIQ
Integrated Processor.
2. Set these fields in the PIC of P2020 QorIQ Integrated Processor:
EIVPRn[PRIORITY] to 0xF (highest priority)
EIDRn[EP]
3. Enable persistent memory feature by setting persistent memory bit inside the FPGA.
4. Any reset may occur except power-up reset.
5. The FPGA generates an interrupt (IRQ_N[11]) to the P2020 QorIQ Integrated Processor.
6. This external interrupt is steered through the PIC of P2020 QorIQ Integrated Processor to
the IRQ_OUT signal.
7. The IRQ_OUT signal from the interrupt controller is then automatically detected by the
DDR controller, which immediately causes main memory to enter self-refresh mode.
8. 1ms after the interrupt signal (IRQ_N[11]) the FPGA asserts the reset signal for at least
50ms.
9. Read persistent memory bit in FPGA.
10. Initialize main memory but do not clear persistent memory area.
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