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Vector Floating-point Programming

6-32

ARM DUI 0068B

6.7.13

FMRRS and FMSRR

Transfer contents between two single-precision floating-point registers and two ARM
registers.

Syntax

FMRRS{

cond

}

, {

}

FMSRR{

cond

} {

where:

cond

is an optional condition code (see

VFP and condition codes

on page 6-8).

are two consecutive VFP single-precision registers.

are the ARM registers. Do not use r15.

Usage

The

FMRRS

instruction transfers the contents of

into

, and the contents of

into

The

FMSRR

instruction transfers the contents of

into

, and the contents of

into

Exceptions

These instructions do not produce any exceptions.

Architectures

These instructions are available in VFPv2 and above.

Examples

FMRRS r2, r3, {s0,s1}
FMSRRNE {s27,s28}, r5, r2

Incorrect examples

FMRRS r2, r3, {s2,s4} ; VFP registers must be consecutive
FMSRR {s5,s6}, r15, r0 ; you must not use r15

Summary of Contents for Developer Suite

Page 2: ...ial form except with the prior written permission of the copyright holder The product described in this document is subject to continuous developments and improvements All particulars of the product and its use contained in this document are given by ARM in good faith However all warranties implied or expressed including but not limited to implied warranties of merchantability or fitness for purpo...

Page 3: ...ntroduction 2 2 2 2 Overview of the ARM architecture 2 3 2 3 Structure of assembly language modules 2 12 2 4 Using the C preprocessor 2 19 2 5 Conditional execution 2 20 2 6 Loading constants into registers 2 25 2 7 Loading addresses into registers 2 30 2 8 Load and store multiple register instructions 2 39 2 9 Using macros 2 48 2 10 Describing data structures with MAP and FIELD directives 2 51 2 ...

Page 4: ...cess instructions 5 4 5 2 Thumb arithmetic instructions 5 15 5 3 Thumb general data processing instructions 5 22 5 4 Thumb branch instructions 5 31 5 5 Thumb software interrupt and breakpoint instructions 5 37 5 6 Thumb pseudo instructions 5 39 Chapter 6 Vector Floating point Programming 6 1 The vector floating point coprocessor 6 4 6 2 Floating point registers 6 5 6 3 Vector and scalar operations...

Page 5: ...01 ARM Limited All rights reserved v Preface This preface introduces the documentation for the ARM Developer Suite ADS assemblers and assembly language It contains the following sections About this book on page vi Feedback on page ix ...

Page 6: ...e following chapters Chapter 1 Introduction Read this chapter for an introduction to the ADS version 1 2 assemblers and assembly language Chapter 2 Writing ARM and Thumb Assembly Language Read this chapter for tutorial information to help you use the ARM assemblers and assembly language Chapter 3 Assembler Reference Read this chapter for reference material about the syntax and structure of the lan...

Page 7: ...internal cross references and citations bold Highlights interface elements such as menu names Also used for emphasis in descriptive lists where appropriate and for ARM processor signal names Further reading This section lists publications from both ARM Limited and third parties that provide additional information on developing code for the ARM family of processors ARM periodically provides updates...

Page 8: ...rmarm pdf ARM ELF specification SWS ESPC 0003 This is supplied in PDF format in install_directory PDF specs ARMELF pdf TIS DWARF 2 specification This is supplied in PDF format in install_directory PDF specs TIS DWARF2 pdf ARM Thumb Procedure Call Specification SWS ESPC 0002 This is supplied in PDF format in install_directory PDF specs ATPCS pdf In addition refer to the following documentation for ...

Page 9: ...rdware platform operating system type and version a small standalone sample of code that reproduces the problem a clear explanation of what you expected to happen and what actually happened the commands you used including any command line options sample output illustrating the problem the version string of the tools including the version number and build numbers Feedback on this book If you have a...

Page 11: ...ARM Limited All rights reserved 1 1 Chapter 1 Introduction This chapter introduces the assemblers provided with ARM Developer Suite ADS version 1 2 It contains the following sections About the ARM Developer Suite assemblers on page 1 2 ...

Page 12: ...ng inline assembler built into the C and C compilers The language that these assemblers take as input is basically the same However there are limitations on what features of the language you can use in the inline assemblers Refer to the Mixing C C and Assembly Language chapter in ADS Developer Guide for further information on the inline assemblers The remainder of this book relates mainly to armas...

Page 13: ...ction on page 2 2 Overview of the ARM architecture on page 2 3 Structure of assembly language modules on page 2 12 Using the C preprocessor on page 2 19 Conditional execution on page 2 20 Loading constants into registers on page 2 25 Loading addresses into registers on page 2 30 Load and store multiple register instructions on page 2 39 Using macros on page 2 48 Describing data structures with MAP...

Page 14: ...al 2 1 1 Code examples There are a number of code examples in this chapter Many of them are supplied in the examples asm directory of the ADS Follow these steps to build link and execute an assembly language file 1 Type armasm g filename s at the command prompt to assemble the file and generate debug tables 2 Type armlink filename o o filename to link the object file and generate an ELF executable...

Page 15: ...ture versions v4T and above define a 16 bit instruction set called the Thumb instruction set The functionality of the Thumb instruction set is a subset of the functionality of the 32 bit ARM instruction set Refer to Thumb instruction set overview on page 2 9 for more information A processor that is executing Thumb instructions is operating in Thumb state A processor that is executing ARM instructi...

Page 16: ...Reference Manual for more information 2 2 4 Registers ARM processors have 37 registers The registers are arranged in partially overlapping banks There is a different register bank for each processor mode The banked registers give rapid context switching for dealing with processor exceptions and privileged operations Refer to ARM Architecture Reference Manual for a detailed description of how regis...

Page 17: ...ine you can copy the link register into the program counter using MOV pc lr During execution r15 does not contain the address of the currently executing instruction The address of the currently executing instruction is typically pc 8 for ARM or pc 4 for Thumb The Current Program Status Register CPSR The CPSR holds copies of the Arithmetic Logic Unit ALU status flags the current processor mode inte...

Page 18: ...e instructions on page 2 7 Multiple register load and store instructions on page 2 7 Status register access instructions on page 2 7 Semaphore instructions on page 2 7 Coprocessor instructions on page 2 7 Branch instructions These instructions are used to branch backwards to form loops branch forward in conditional structures branch to subroutines change the processor from ARM state to Thumb state...

Page 19: ...extend a 16 bit halfword or an 8 bit byte Multiple register load and store instructions These instructions load or store any subset of the general purpose registers from or to memory Refer to Load and store multiple register instructions on page 2 39 for a detailed description of these instructions Status register access instructions These instructions move the contents of the CPSR or an SPSR to o...

Page 20: ...etween Refer to Conditional execution on page 2 20 for a detailed description Register access In ARM state all instructions can access r0 to r14 and most also allow access to r15 pc The MRS and MSR instructions can move the contents of the CPSR and SPSRs to a general purpose register where they can be manipulated by normal data processing operations Refer to MRS on page 4 73 and MSR on page 4 74 f...

Page 21: ...truction set and how Thumb instructions differ from their ARM counterparts 2 2 8 Thumb instruction capabilities The following general points apply to Thumb instructions Conditional execution Register access Access to the barrel shifter on page 2 10 Conditional execution The conditional branch instruction is the only Thumb instruction that can be executed conditionally on the value of the ALU statu...

Page 22: ...instructions no Thumb semaphore instructions and no Thumb instructions to access the CPSR or SPSR Branch instructions These instructions are used to branch backwards to form loops branch forward in conditional structures branch to subroutines change the processor from Thumb state to ARM state Program relative branches particularly conditional branches are more limited in range than in ARM code and...

Page 23: ...from or to memory In Thumb state they can only access registers r0 to r7 Multiple register load and store instructions LDM and STM load from memory and store to memory any subset of the registers in the range r0 to r7 PUSH and POP instructions implement a full descending stack using the stack pointer r13 as the base In addition to transferring r0 to r7 PUSH can store the link register and POP can ...

Page 24: ...if there is no label All three sections of the source line are optional You can use blank lines to make your code more readable Case rules Instruction mnemonics directives and symbolic register names can be written in uppercase or lowercase but not mixed Line length To make source files easier to read a long line of source can be split onto several lines by placing a backslash character at the end...

Page 25: ...er sections are calculated at link time when the linker has allocated specific locations in memory for each section Local labels Local labels are a subclass of label A local label begins with a number in the range 0 99 Unlike other labels a local label can be defined many times Local labels are useful when you are generating labels with a macro When the assembler finds a reference to a local label...

Page 26: ...d FALSE must be written as TRUE and FALSE Characters Character constants consist of opening and closing single quotes enclosing either a single character or an escaped character using the standard C escape characters Strings Strings consist of opening and closing double quotes enclosing characters and spaces If double quotes or dollar signs are used within a string as literal text characters they ...

Page 27: ...parameters MOV r1 3 ADD r0 r0 r1 r0 r0 r1 stop MOV r0 0x18 angel_SWIreason_ReportException LDR r1 0x20026 ADP_Stopped_ApplicationExit SWI 0x123456 ARM semihosting SWI END Mark end of file ELF sections and the AREA directive ELF sections are independent named indivisible sequences of code or data A single code section is the minimum required to produce an application The output of an assembly or co...

Page 28: ...d In applications containing C code an entry point is also contained within the C library initialization code Initialization code and exception handlers also contain entry points Application execution The application code in Example 2 1 on page 2 15 begins executing at the label start where it loads the decimal values 10 and 3 into registers r0 and r1 These registers are added together and the res...

Page 29: ...ults back to the callers Note Calls between separately assembled or compiled modules must comply with the restrictions and conventions defined by the procedure call standard Refer to the Using the Procedure Call Standard in ADS Developer Guide for more information Example 2 2 shows a subroutine that adds the values of its two parameters and returns a result in r0 It is supplied as subrout s in the...

Page 30: ...t MOV r0 10 Set up parameters MOV r1 3 BL doadd Call subroutine stop MOV r0 0x18 angel_SWIreason_ReportException LDR r1 0x20026 ADP_Stopped_ApplicationExit SWI 0xAB Thumb semihosting SWI doadd ADD r0 r0 r1 Subroutine code MOV pc lr Return from subroutine END Mark end of file CODE32 and CODE16 directives These directives instruct the assembler to assemble subsequent instructions as ARM CODE32 or Th...

Page 31: ...emble it See ADS Compilers and Libraries Guide armasm correctly interprets line commands in the resulting file It can generate error messages and debug_line tables using the information in the line commands Example 2 4 shows the commands you write to preprocess and assemble a file sourcefile s In this example the preprocessor outputs a file called preprocessed s and armasm assembles preprocessed s...

Page 32: ...e them conditional In ARM state you can update the ALU status flags in the CPSR on the result of a data operation execute several other data operations without updating the flags execute following instructions or not according to the state of the flags updated in the first operation In Thumb state most data operations always update the flags and conditional execution can only be achieved using the...

Page 33: ... r0 r1 r2 and update flags CMP r0 r1 update flags based on r0 r1 Table 2 1 Condition code suffixes Suffix Flags Meaning EQ Z set Equal NE Z clear Not equal CS HS C set Higher or same unsigned CC LO C clear Lower unsigned MI N set Negative PL N clear Positive or zero VS V set Overflow VC V clear No overflow HI C set and Z clear Higher unsigned LS C clear or Z set Lower or same unsigned GE N and V t...

Page 34: ...ction hardware In systems using these processors the pipeline only needs to be flushed and refilled when there is a misprediction 2 5 4 Example of the use of conditional execution This example uses two implementations of Euclid s Greatest Common Divisor gcd algorithm It demonstrates how you can use conditional execution to improve code density and execution speed The detailed analysis of execution...

Page 35: ... SUBLT r1 r1 r0 BNE gcd In addition to improving code size this code executes faster in most cases Table 2 2 and Table 2 3 on page 2 24 show the number of cycles used by each implementation for the case where r0 equals 1 and r1 equals 2 In this case replacing branches with conditional execution of all instructions saves three cycles The conditional version of the code executes in the same number o...

Page 36: ...umb version runs faster than the second ARM implementation because only one memory access is required for each Thumb instruction whereas each ARM instruction requires two fetches Branch prediction and caches To optimize code for execution speed you need detailed knowledge of the instruction timings branch prediction logic and cache behavior of your target system Refer to ARM Architecture Reference...

Page 37: ... into a register with a data load but there are more direct and efficient ways to load many commonly used constants You can also include many commonly used constants directly as operands within data processing instructions without a separate load operation at all The following sections describe how to use the MOV and MVN instructions to load a range of immediate values see Direct loading with MOV ...

Page 38: ... is useful if the value is an assembly time variable If you write an instruction with a constant that cannot be constructed the assembler reports the error Immediate n out of range for this operation The range of values shown in Table 2 4 can also be used as one of the operands in data processing operations You cannot use their bitwise complements as operands and you cannot use them as operands in...

Page 39: ...it numeric constant in a single instruction Use this pseudo instruction to generate constants that are out of range of the MOV and MVN instructions The LDR pseudo instruction generates the most efficient code for a specific constant If the constant can be constructed with a MOV or MVN instruction the assembler generates the appropriate instruction If the constant cannot be constructed with a MOV o...

Page 40: ...ool is out of range the assembler generates an error message In this case you must use the LTORG directive to place an additional literal pool in the code Place the LTORG directive after the failed LDR pseudo instruction and within 4KB ARM or 1KB Thumb Refer to LTORG on page 7 14 for a detailed description You must place literal pools where the processor does not attempt to execute them as instruc...

Page 41: ... LDR r4 0x66666666 If this is uncommented it fails because Literal Pool 2 is out of reach MOV pc lr LargeTable SPACE 4200 Starting at the current location clears a 4200 byte area of memory to zero END Literal Pool 2 is empty 2 6 3 Loading floating point constants You can load any single precision or double precision floating point constant in a single instruction using the FLD pseudo instructions ...

Page 42: ...in a specified general purpose register Refer to Describing data structures with MAP and FIELD directives on page 2 51 for information on specifying register relative expressions The assembler converts an ADR rn label pseudo instruction by generating a single ADD or SUB instruction that loads the address if it is in range an error message if the address cannot be reached in a single instruction Th...

Page 43: ...rectory of the ADS Refer to Code examples on page 2 2 for instructions on how to assemble link and execute the example The instructions listed in the comments are the ARM instructions generated by the assembler Example 2 6 AREA adrlabel CODE READONLY ENTRY Mark first instruction to execute Start BL func Branch to subroutine stop MOV r0 0x18 angel_SWIreason_ReportException LDR r1 0x20026 ADP_Stoppe...

Page 44: ...t argument2 argument3 argument1 1 Result argument2 argument3 The jump table is implemented with the following instructions and assembler directives EQU Is an assembler directive It is used to give a value to a symbol In this example it assigns the value 2 to num When num is used elsewhere in the code the value 2 is substituted Using EQU in this way is similar to using define to define a constant i...

Page 45: ...ee parameters MOV r1 3 MOV r2 2 BL arithfunc Call the function stop MOV r0 0x18 angel_SWIreason_ReportException LDR r1 0x20026 ADP_Stopped_ApplicationExit SWI 0x123456 ARM semihosting SWI arithfunc Label the function CMP r0 num Treat function code as unsigned integer MOVHS pc lr If code is num then simply return ADR r3 JumpTable Load address of jump table LDR pc r3 r0 LSL 2 Jump to the appropriate...

Page 46: ... pc using an LDR instruction do an inline shift of a value held in a register Example 2 8 Thumb code jump table AREA Jump CODE READONLY CODE16 Following code is Thumb code num EQU 2 ENTRY start MOV r0 0 MOV r1 3 MOV r2 2 BL arithfunc stop MOV r0 0x18 LDR r1 0x20026 SWI 0xAB Thumb semihosting SWI arithfunc CMP r0 num BHS exit MOV pc lr cannot be conditional ADR r3 JumpTable LSL r0 r0 2 3 instructio...

Page 47: ...ADR and ADRL pseudo instructions you can use LDR with labels that are outside the current section If the label is outside the current section the assembler places a relocation directive in the object code when the source file is assembled The relocation directive instructs the linker to resolve the address at link time The address remains valid wherever the linker places the section containing the...

Page 48: ...set into Literal Pool 1 MOV pc lr Return LTORG Literal Pool 1 func2 LDR r3 Darea 6000 LDR r3 PC offset into Literal Pool 1 sharing with previous literal LDR r4 Darea 6004 If uncommented produces an error as Literal Pool 2 is out of range MOV pc lr Return Darea SPACE 8000 Starting at the current location clears a 8000 byte area of memory to zero END Literal Pool 2 is out of range of the LDR instruc...

Page 49: ...R instructions use post indexed addressing to update their address registers For example the instruction LDRB r2 r1 1 loads r2 with the contents of the address pointed to by r1 and then increments r1 by 1 Example 2 10 String copy AREA StrCopy CODE READONLY ENTRY Mark first instruction to execute start LDR r1 srcstr Pointer to first string LDR r0 dststr Pointer to second string BL strcopy Call subr...

Page 50: ...I 0068B Converting to Thumb There is no post indexed addressing mode for Thumb LDR and STR instructions Because of this you must use an ADD instruction to increment the address register after the LDR and STR instructions For example LDRB r2 r1 load register 2 ADD r1 1 increment the address in register 1 ...

Page 51: ... instructions include Smaller code size A single instruction fetch overhead rather than many instruction fetches On uncached ARM processors the first word of data transferred by a load or store multiple is always a nonsequential memory cycle but all subsequent words transferred can be sequential memory cycles Sequential memory cycles are faster in most systems Note The lowest numbered register is ...

Page 52: ...s the starting address for the load operation Do not specify r15 pc as the base register specifies base register write back If this is specified the address in the base register is updated after the transfer It is decremented or incremented by one word for each register in the register list register list is a comma delimited list of symbolic register names and register ranges enclosed in braces Th...

Page 53: ...e four different addressing modes The base register can be incremented or decremented by one word for each register in the operation and the increment or decrement can occur before or after the operation The suffixes for these options are IA Increment after IB Increment before DA Decrement after DB Decrement before There are alternative addressing mode suffixes that are easier to use for stack ope...

Page 54: ...rom a low address and progressing to a higher address an ascending stack Full or empty The stack pointer can either point to the last item in the stack a full stack or the next free space on the stack an empty stack To make it easier for the programmer stack oriented suffixes can be used instead of the increment or decrement and before or after suffixes Refer to Table 2 5 for a list of stack orien...

Page 55: ...ausing the return address to be lost If you do this you can also return from a subroutine by popping the pc off the stack at exit instead of popping lr and then moving that value into the pc For example subroutine STMFD sp r5 r7 lr Push work registers and lr code BL somewhere_else code LDMFD sp r5 r7 pc Pop work registers and pc Note Use this with care in mixed ARM and Thumb systems In ARM archite...

Page 56: ...n SUBS r2 r2 1 decrement the counter BNE wordcopy copy more stop MOV r0 0x18 angel_SWIreason_ReportException LDR r1 0x20026 ADP_Stopped_ApplicationExit SWI 0x123456 ARM semihosting SWI AREA BlockData DATA READWRITE src DCD 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 dst DCD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 END This module can be made more efficient by using LDM and STM for as much of the copyin...

Page 57: ...4 r11 Save some working registers octcopy LDMIA r0 r4 r11 Load 8 words from the source STMIA r1 r4 r11 and put them at the destination SUBS r3 r3 1 Decrement the counter BNE octcopy copy more LDMFD sp r4 r11 Don t need these now restore originals copywords ANDS r2 r2 7 Number of odd words to copy BEQ stop No words left to copy wordcopy LDR r3 r0 4 Load a word from the source and STR r3 r1 4 store ...

Page 58: ... optionally the link register onto the stack and to pop any subset of the low registers and optionally the pc off the stack The base address of the stack is held in r13 Examples of these instructions are PUSH r0 r3 POP r0 r3 PUSH r4 r7 lr POP r4 r7 pc The optional addition of the lr or pc to the register list provides support for subroutine entry and exit The stack is always full descending Thumb ...

Page 59: ...umber of four word multiples BEQ copywords Less than four words to move PUSH r4 r7 Save some working registers quadcopy LDMIA r0 r4 r7 Load 4 words from the source STMIA r1 r4 r7 and put them at the destination SUB r3 1 Decrement the counter BNE quadcopy copy more POP r4 r7 Don t need these now restore originals copywords MOV r3 3 Bottom two bits represent number AND r2 r3 of odd words left to cop...

Page 60: ... for more details 2 9 1 Test and branch macro example A test and branch operation requires two ARM instructions to implement You can define a macro definition such as this MACRO label TestAndBranch dest reg cc label CMP reg 0 B cc dest MEND The line after the MACRO directive is the macro prototype statement The macro prototype statement defines the name TestAndBranch you use to invoke the macro It...

Page 61: ...uring the calculation Example 2 14 MACRO Lab DivMod Div Top Bot Temp ASSERT Top Bot Produce an error message if the ASSERT Top Temp registers supplied are ASSERT Bot Temp not all different IF Div ASSERT Div Top These three only matter if Div ASSERT Div Bot is not null ASSERT Div Temp ENDIF Lab MOV Temp Bot Put divisor in Temp CMP Temp Top LSR 1 double it until 90 MOVLS Temp Temp LSL 1 2 Temp Top C...

Page 62: ... 2 15 shows the code that this macro produces if it is invoked as follows ratio DivMod r0 r5 r4 r2 Example 2 15 ASSERT r5 r4 Produce an error if the ASSERT r5 r2 registers supplied are ASSERT r4 r2 not all different ASSERT r0 r5 These three only matter if Div ASSERT r0 r4 is not null ASSERT r0 r2 ratio MOV r2 r4 Put divisor in Temp CMP r2 r5 LSR 1 double it until 90 MOVLS r2 r2 LSL 1 2 r2 r5 CMP r...

Page 63: ...sed to describe multiple instances of the same structure make it easy to access data efficiently The MAP directive specifies the base address of the data structure Refer to MAP on page 7 15 for further information The FIELD directive specifies the amount of memory required for a data item and can give the data item a label It is repeated for each data item in the structure Refer to FIELD on page 7...

Page 64: ...wing instructions MOV r9 4096 LDR r4 r9 constb The labels are relative to the start of the data structure The register used to hold the start address of the map r9 in this case is called the base register There are likely to be many LDR or STR instructions accessing data in this data structure This map does not contain the location of the data structure The location of the structure is determined ...

Page 65: ...ple 2 17 MAP 0 r9 consta FIELD 4 consta uses four bytes located at offset 0 from r9 constb FIELD 4 constb uses four bytes located at offset 4 x FIELD 8 x uses eight bytes located at offset 8 y FIELD 8 y uses eight bytes located at offset 16 string FIELD 256 string is up to 256 bytes long starting at offset 24 Using the map in Example 2 17 you can access the data structure wherever it is ADR r9 dat...

Page 66: ... range after linking Example 2 18 shows a program fragment with such a map It includes a directive which allocates space in memory for the data structure and an instruction which accesses it Example 2 18 datastruc SPACE 280 reserves 280 bytes of memory for datastruc MAP datastruc consta FIELD 4 constb FIELD 4 x FIELD 8 y FIELD 8 string FIELD 256 code LDR r2 constb LDR r2 pc offset In this case the...

Page 67: ... values of MaxStrLen and ArrayLen If these values are too large the structure overruns the end of available memory Example 2 19 uses an EQU directive to define the end of available memory a FIELD directive with an operand of 0 to label the end of the data structure An ASSERT directive checks that the end of the data structure does not overrun the available memory Example 2 19 StartOfData EQU 0x100...

Page 68: ...y MAP and FIELD directives do not allocate any memory for the structures they define You could insert a dummy FIELD 1 after Char3 FIELD 1 However this makes maintenance difficult if you change the number of character variables You must recalculate the right amount of padding each time Example 2 21 on page 2 57 shows a better way of adjusting the padding The example uses a FIELD directive with a 0 ...

Page 69: ... Example 2 21 StartOfData EQU 0x1000 EndOfData EQU 0x2000 MAP StartOfData Char FIELD 1 Char2 FIELD 1 Char3 FIELD 1 EndOfChars FIELD 0 Padding FIELD EndOfChars AND 3 Integer FIELD 4 Integer2 FIELD 4 String FIELD MaxStrLen Array FIELD ArrayLen 8 BitMask FIELD 4 EndOfUsedData FIELD 0 ASSERT EndOfUsedData EndOfData ...

Page 70: ...ssion to a register based symbol to get another register based symbol Subtracting an ordinary numeric expression from a register based symbol to get another register based symbol Subtracting a register based symbol from another register based symbol to get an ordinary numeric expression Do not do this unless the two register based symbols are based on the same register Otherwise you have a combina...

Page 71: ...mory named origin oldloc and newloc typedef struct Point float x y z Point Point origin oldloc newloc The following assembly language code is equivalent to the typedef statement above PointBase RN r11 MAP 0 PointBase Point_x FIELD 4 Point_y FIELD 4 Point_z FIELD 4 The following assembly language code allocates space in memory This is equivalent to the last line of C code origin SPACE 12 oldloc SPA...

Page 72: ...QU 0x2000 MAP StartOfData Integer FIELD 4 String FIELD MaxStrLen Array FIELD ArrayLen 8 BitMask FIELD 4 EndOfUsedData FIELD 0 ASSERT EndOfUsedData EndOfData If you want the equivalent of the C code Integer 1 String BitMask 0xA000000A With the definitions from Example 2 22 the assembly language code can be as shown in Example 2 23 Example 2 23 MOV r0 1 LDR r1 Integer STR r0 r1 MOV r0 0 LDR r1 Strin...

Page 73: ...0x1000 EndOfData EQU 0x2000 DataAreaBase RN r11 MAP 0 DataAreaBase StartOfUsedData FIELD 0 Integer FIELD 4 String FIELD MaxStrLen Array FIELD ArrayLen 8 BitMask FIELD 4 EndOfUsedData FIELD 0 UsedDataLen EQU EndOfUsedData StartOfUsedData ASSERT UsedDataLen EndOfData StartOfData AREA code CODE LDR DataAreaBase StartOfData MOV r0 1 STR r0 Integer MOV r0 0 STRB r0 String MOV r0 0xA000000A STRB r0 BitM...

Page 74: ...Using MAP offset reg followed by label FIELD 0 makes label into a register based symbol with register part reg and numeric part offset Example 2 25 shows this Example 2 25 StartOfIOArea EQU 0x1000000 SendFlag_Abs EQU 0x1000000 SendData_Abs EQU 0x1000004 RcvFlag_Abs EQU 0x1000008 RcvData_Abs EQU 0x100000C IOAreaBase RN r11 MAP SendFlag_Abs StartOfIOArea IOAreaBase SendFlag FIELD 0 MAP SendData_Abs ...

Page 75: ...e oldloc structure and to the newloc one Repeatedly changing the base register would be inefficient Instead use a non register based map and set up two pointers in two different registers as in Example 2 26 Example 2 26 MAP 0 Non register based relative map used twice for Pointx FIELD 4 old and new data at oldloc and newloc Pointy FIELD 4 oldloc and newloc are labels for Pointz FIELD 4 memory allo...

Page 76: ...s require the data elements in the structure to be contiguous in memory and to be in a specific order If the order of the elements is changed or a new element is added the program is broken in a way that cannot be detected by the assembler There are several methods for avoiding problems such as this Example 2 27 shows a sample structure Example 2 27 MiscBase RN r10 MAP 0 MiscBase MiscStart FIELD 0...

Page 77: ...single array element In this case you must amend the code The first remedy is to comment the structure to prevent changes affecting this section Misc_I FIELD 4 Do not split reorder Misc_J FIELD 4 these 3 elements STM Misc_K FIELD 4 and LDM instructions used If the code is strongly commented no deliberate changes are likely to be made that affect the workings of the program Unfortunately mistakes c...

Page 78: ...use either flat or call graph profiling Refer to Frame description directives on page 7 33 for details of these directives The assembler uses these directives to insert DWARF2 debug frame information into the object file in ELF format that it produces This information is required by the debuggers for stack unwinding and for profiling Refer to the Using the Procedure Call Standard chapter in ADS De...

Page 79: ...ines on page 3 8 Predefined register and coprocessor names on page 3 9 Built in variables on page 3 10 Symbols on page 3 12 Expressions literals and operators on page 3 18 This chapter does not explain how to write ARM assembly language See Chapter 2 Writing ARM and Thumb Assembly Language for tutorial information It also does not describe the instructions directives or pseudo instructions See the...

Page 80: ...sembler to interpret instructions as ARM instructions This is the default apcs none qualifier qualifier specifies whether you are using the ARM Thumb Procedure Call Standard ATPCS It can also specify some attributes of code sections See ADS Developer Guide for more information about the ATPCS none specifies that inputfile does not use ATPCS ATPCS registers are not set up Qualifiers are not allowed...

Page 81: ...it checking bigend instructs the assembler to assemble code suitable for a big endian ARM The default is littleend littleend instructs the assembler to assemble code suitable for a little endian ARM checkreglist instructs the assembler to check RLIST LDM and STM register lists to ensure that all registers are provided in increasing register number order A warning is given if registers are not list...

Page 82: ...nd selection of libraries accordingly Valid options are none Selects no floating point option This makes your assembled object file compatible with any other object file vfp This is a synonym for fpu vfpv1 vfpv1 Selects hardware vector floating point unit conforming to architecture VFPv1 vfpv2 Selects hardware vector floating point unit conforming to architecture VFPv2 fpa Selects hardware Floatin...

Page 83: ...the behavior of list noterse turns the terse flag off When this option is on lines skipped due to conditional assembly do not appear in the listing If the terse option is off these lines do appear in the listing The default is on width sets the listing page width The default is 79 characters length sets the listing page length Length zero means an unpaged listing The default is 66 lines xref instr...

Page 84: ...e o predefine directive instructs the assembler to pre execute one of the SET directives You must enclose directive in quotes See SETA SETL and SETS on page 7 7 The assembler executes a corresponding GBLL GBLS or GBLA directive to define the variable before setting its value The variable name is case sensitive Note The command line interface of your system might require you to enter special charac...

Page 85: ... cycles required for the slowest memory or peripheral access This is typically much greater than the latency introduced by multiple register transfers unsafe allows assembly of a file containing instructions that are not available on the specified architecture and processor It changes corresponding error messages to warning messages It also suppresses warnings about operator precedence see Binary ...

Page 86: ... You can write directives in all upper case as in this manual Alternatively you can write directives in all lower case You must not write a directive in mixed upper and lower case You can use blank lines to make your code more readable symbol is usually a label see Labels on page 3 15 In instructions and pseudo instructions it is always a label In some directives it is a symbol for a variable or a...

Page 87: ...register r12 sp and SP stack pointer r13 lr and LR link register r14 pc and PC program counter r15 3 3 2 Predeclared program status register names The following program status register names are predeclared cpsr and CPSR current program status register spsr and SPSR saved program status register 3 3 3 Predeclared floating point register names The following floating point register names are predecl...

Page 88: ...ian mode or little if it is in little endian mode CODESIZE Is a synonym for CONFIG CPU Holds the name of the selected cpu The default is ARM7TDMI If an architecture was specified in the command line cpu option CPU holds the value Generic ARM FPU Holds the name of the selected fpu The default is SoftVFP ARCHITECTURE Holds the name of the selected ARM architecture PCSTOREOFFSET Is the offset between...

Page 89: ... armasm version at assembly time The built in variable ARMASM VERSION can be used to distinguish between versions of armasm from ADS1 0 onwards However previous versions of armasm did not have this built in variable If you need to build both ADS and SDT versions of your code you can test for the built in variable ads version Use code similar to the following IF DEF ads version code for ADS ELSE co...

Page 90: ...s see Local labels on page 3 16 Symbol names are case sensitive All characters in the symbol name are significant Symbol names must be unique within their scope Symbols must not use built in variable names or predefined symbol names see Predefined register and coprocessor names on page 3 9 and Built in variables on page 3 10 Symbols must not use the same name as instruction mnemonics or directives...

Page 91: ... string expression see String expressions on page 3 19 Use the GBLA GBLL GBLS LCLA LCLL and LCLS directives to declare symbols representing variables and assign values to them using the SETA SETL and SETS directives See GBLA GBLL and GBLS on page 7 4 LCLA LCLL and LCLS on page 7 6 SETA SETL and SETS on page 7 7 3 5 3 Numeric constants Numeric constants are 32 bit integers You can set them using un...

Page 92: ...he variable name if the following character would be permissible in a symbol name see Symbol naming rules on page 3 12 You must set the contents of the variable before you can use it If you need a that you do not want to be substituted use This is converted to a single You can include a variable with a prefix in a string Substitution occurs in the same way as anywhere else Substitution does not oc...

Page 93: ...on or on one of the data definition directives See DCB on page 7 18 DCD and DCDU on page 7 19 DCFD and DCFDU on page 7 21 DCFS and DCFSU on page 7 22 DCI on page 7 23 DCQ and DCQU on page 7 24 DCW and DCWU on page 7 25 Register relative labels These represent a named register plus a numeric constant They are most often used to access data in data sections You can define them with a storage map You...

Page 94: ...l label even within the same scope By default the assembler links a local label reference to the most recent local label of the same number if there is one within the scope the next following local label of the same number if there is not a preceding one within the scope Use the optional parameters to modify this search pattern if required Syntax The syntax of a local label is n routname The synta...

Page 95: ...ted All rights reserved 3 17 If routname is specified in either a label or a reference to a label the assembler checks it against the name of the nearest preceding ROUT directive If it does not match the assembler generates an error message and the assembly fails ...

Page 96: ...String expressions on page 3 19 String literals on page 3 19 Numeric expressions on page 3 20 Numeric literals on page 3 21 Floating point literals on page 3 22 Register relative and program relative expressions on page 3 23 Logical expressions on page 3 23 Logical literals on page 3 23 Operator precedence on page 3 24 Unary operators on page 3 26 Binary operators on page 3 28 ...

Page 97: ... cannot exceed 512 characters in length It can be of zero length Example improb SETS literal CC strvar2 LEFT 4 sets the variable improb to the value literal with the left most four characters of the contents of string variable strvar2 appended 3 6 2 String literals String literals consist of a series of characters contained between double quote characters The length of a string literal is restrict...

Page 98: ...page 7 7 Numeric expressions can contain register relative or program relative expressions if the overall expression evaluates to a value that does not include a register or the program counter Numeric expressions evaluate to 32 bit integers You can interpret them as unsigned numbers in the range 0 to 232 1 or signed numbers in the range 231 to 231 1 However the assembler makes no distinction betw...

Page 99: ...nclusive followed by an underscore character base n digits is a sequence of characters using only the digits 0 to n 1 character is any single character except a single quote Use if you require a single quote In this case the value of the numeric literal is the numeric code of the character You must not use any other characters The sequence of characters must evaluate to an integer in the range 0 t...

Page 100: ... sequences of characters using only the digits 0 to 9 and the letters A to F or a to f These forms correspond to the internal representation of the numbers in the computer Use these forms to enter infinities and NaNs or if you want to be sure of the exact bit patterns you are using The range for single precision floating point values is maximum 3 40282347e 38 minimum 1 17549435e 38 The range for d...

Page 101: ...numeric expression Example LDR r4 data 4 n n is an assembly time variable code MOV pc lr data DCD value0 n 1 DCD directives DCD valuen data 4 n points here more DCD directives 3 6 7 Logical expressions Logical expressions consist of combinations of logical literals TRUE or FALSE logical variables Boolean operators relations and parentheses see Boolean operators on page 3 31 Relations consist of co...

Page 102: ...ecedence are evaluated from left to right Note The order of precedence is not exactly the same as in C For example 1 2 SHR 3 evaluates as 1 2 SHR 3 1 in armasm The equivalent expression in C evaluates as 1 2 3 0 You are recommended to use brackets to make the precedence explicit Table 3 2 shows the order of precedence of operators in armasm and a comparison with the order in C If your code contain...

Page 103: ... at the top of the list The highest precedence operators are evaluated first Operators of equal precedence are evaluated from left to right AND OR EOR LAND LOR LEOR Table 3 3 Operator precedence in C C precedence unary operators as binary operators Table 3 2 Operator precedence in armasm armasm precedence equivalent C operators ...

Page 104: ...EX INDEX A If A is a register relative expression INDEX returns the offset from that base register INDEX is most useful in macros and A A Unary plus Unary minus and can act on numeric and program relative expressions LEN LEN A Length of string A CHR CHR A One character string ASCII code A STR STR A Hexadecimal string of A STR returns an eight digit hexadecimal string corresponding to a numeric exp...

Page 105: ...T_19_12 and SB_OFFSET_11_ 0 MyIndex EQU 0 AREA area1 CODE LDR IP SB 0 LDR IP IP MyIndex ADD IP IP SB_OFFSET_19_12 label LDR PC IP SB_OFFSET_11_0 label AREA area2 DATA label IMPORT FunctionAddress DCD FunctionAddress END These operators can only be used in ADD and LDR instructions They can only be used in the way shown ...

Page 106: ...s have the highest precedence of all binary operators They act only on numeric expressions Table 3 5 shows the multiplicative operators String manipulation operators Table 3 6 shows the string manipulation operators In the two slicing operators LEFT and RIGHT A must be a string B must be a numeric expression In CC A and B must both be strings Table 3 5 Multiplicative operators Operator Usage Expla...

Page 107: ...ogical operators act on numeric expressions The operation is performed bitwise that is independently on each bit of the operands to produce the result Table 3 8 shows addition subtraction and logical operators Table 3 7 Shift operators Operator Usage Explanation ROL A ROL B Rotate A left by B bits ROR A ROR B Rotate A right by B bits SHL A SHL B Shift A left by B bits SHR A SHR B Shift A right by ...

Page 108: ...trings Strings are sorted using ASCII ordering String A is less than string B if it is a leading substring of string B or if the left most character in which the two strings differ is less in string A than in string B Arithmetic values are unsigned so the value of 0 1 is FALSE Table 3 9 Relational operators Operator Usage Explanation A B A equal to B A B A greater than B A B A greater than or equa...

Page 109: ...hey perform the standard logical operations on their operands In all three cases both A and B must be expressions that evaluate to either TRUE or FALSE Table 3 10 shows the Boolean operators Table 3 10 Boolean operators Operator Usage Explanation LAND A LAND B Logical AND of A and B LOR A LOR B Logical OR of A and B LEOR A LEOR B Logical Exclusive OR of A and B ...

Page 111: ... 4 ARM memory access instructions on page 4 6 ARM general data processing instructions on page 4 23 ARM multiply instructions on page 4 39 ARM saturating arithmetic instructions on page 4 55 ARM branch instructions on page 4 57 ARM coprocessor instructions on page 4 62 Miscellaneous ARM instructions on page 4 71 ARM pseudo instructions on page 4 78 See to Table 4 1 on page 4 2 to locate individual...

Page 112: ...e 4 38 5 CMN CMP Compare negative Compare page 4 34 All EOR Exclusive OR page 4 30 All LDC LDC2 Load coprocessor page 4 67 2 5 LDM Load multiple registers page 4 18 All LDR Load register page 4 6 All MAR Move from registers to 40 bit accumulator page 4 77 XScalec MCR MCR2 MCRR Move from register s to coprocessor page 4 64 2 5 5Ed MIA MIAPH MIAxy Multiply with internal 40 bit accumulate page 4 53 X...

Page 113: ...ULxy Signed multiply 32 16 x 16 page 4 44 5ExPe STC STC2 Store coprocessor page 4 67 2 5ExPe STM Store multiple registers page 4 18 All STR Store register page 4 6 All SUB Subtract page 4 27 All SWI Software interrupt page 4 72 All SWP Swap registers and memory page 4 22 3 TEQ TST Test equivalence Test page 4 36 All UMLAL UMULL Unsigned MLA MUL 64 32 x 32 64 page 4 42 Mf a n available in ARM archi...

Page 114: ...suffix as shown in the syntax description for the instruction Some instructions CMP CMN TST and TEQ do not require the S suffix Their only function is to update the flags They always update the flags Flags are preserved until updated A conditional instruction which is not executed has no effect on the flags Table 4 2 ARM condition codes Suffix Flags Meaning EQ Z set Equal NE Z clear Not equal CS H...

Page 115: ...only exists in E variants of ARM architecture v5 and above It is used to detect saturation in special saturating arithmetic instructions see QADD QSUB QDADD and QDSUB on page 4 55 or overflow in certain multiply instructions see SMLAxy on page 4 46 and SMLAWy on page 4 49 The Q flag is a sticky flag Although these instructions can set the flag they cannot clear it You can execute a series of such ...

Page 116: ... Load register signed 8 bit bytes and signed and unsigned 16 bit halfwords Store register 16 bit halfwords LDR and STR doublewords on page 4 15 Load two consecutive registers and store two consecutive registers LDM and STM on page 4 18 Load and store multiple registers PLD on page 4 20 Cache preload SWP on page 4 22 Swap data between registers and memory There is also an LDR pseudo instruction see...

Page 117: ...r or STR Store Register cond is an optional condition code see Conditional execution on page 4 4 B is an optional suffix If B is present the least significant byte of Rd is transferred If op is LDR the other bytes of Rd are cleared Otherwise a 32 bit word is transferred T is an optional suffix If T is present the memory system treats the access as though the processor was in User mode even if it i...

Page 118: ...ue in Rn is used as the address for the transfer Pre indexed offset The offset is applied to the value in Rn before the data transfer takes place The result is used as the memory address for the transfer If the suffix is used the result is written back into Rn Rn must not be r15 if the suffix is used Program relative This is an alternative version of the pre indexed form The assembler calculates t...

Page 119: ...se the offset is added to Rn expr is an expression evaluating to an integer in the range 4095 to 4095 This is often a numeric constant see examples below Rm is a register containing a value to be used as the offset Rm must not be r15 shift is an optional shift to be applied to Rm It can be any one of ASR n arithmetic shift right n bits 1 n 32 LSL n logical shift left n bits 0 n 31 LSR n logical sh...

Page 120: ...data are loaded from the resulting address 3 The loaded data is rotated right by one two or three bytes according to bits 1 0 of the address For a little endian memory system this causes the addressed byte to occupy the least significant byte of the register For a big endian memory system it causes the addressed byte to occupy bits 31 24 if bit 0 of the address is 0 bits 15 8 if bit 0 of the addre...

Page 121: ...embled for a particular processor the value of the constant is available in armasm as PCSTOREOFFSET Architectures These instructions are available in all versions of the ARM architecture In T variants of ARM architecture v5 and above a load to r15 causes a change to executing Thumb instructions if bit 0 of the value loaded is set Examples LDR r8 r10 loads r8 from the address in r10 LDRNE r2 r5 960...

Page 122: ...set pre indexed offset program relative post indexed offset The syntax of the four forms in the same order are op cond type Rd Rn op cond type Rd Rn Offset op cond type Rd label op cond type Rd Rn Offset where op is either LDR or STR cond is an optional condition code see Conditional execution on page 4 4 type must be one of SH for Signed Halfword LDR only H for unsigned Halfword SB for Signed Byt...

Page 123: ...result is used as the memory address for the transfer If the suffix is used the result is written back into Rn Program relative This is an alternative version of the pre indexed form The assembler calculates the offset from the PC for you and generates a pre indexed instruction with the PC as Rn You cannot use the suffix Post indexed offset The value in Rn is used as the memory address for the tra...

Page 124: ...word aligned 16 bit load corrupts Rd a non halfword aligned 16 bit save corrupts two bytes at address and address 1 Loading to r15 You cannot load halfwords or bytes to r15 Architectures These instructions are available in ARM architecture v4 and above Examples LDREQSH r11 r6 conditionally loads r11 with a 16 bit halfword from the address in r6 Sign extends to 32 bits LDRH r1 r0 22 load r1 with a ...

Page 125: ...onal condition code see Conditional execution on page 4 4 Rd is one of the ARM registers to load or save The other one is R d 1 Rd must be an even numbered register and not r14 Rn is the register on which the memory address is based Rn must not be the same as Rd or R d 1 unless the instruction is either zero offset pre indexed without writeback Offset is an offset applied to the value in Rn see Of...

Page 126: ...xed offset The value in Rn is used as the memory address for the transfer The offset is applied to the value in Rn after the transfer takes place The result is written back into Rn Offset syntax Both pre indexed and post indexed offsets can be either of the following expr Rm where is an optional minus sign If is present the offset is subtracted from Rn Otherwise the offset is added to Rn expr is a...

Page 127: ...rd aligned 64 bit transfers cause an alignment exception if alignment checking is enabled Architectures These instructions are available in E variants of ARM architecture v5 and above Examples LDRD r6 r11 LDRMID r4 r7 r2 STRD r4 r9 24 STRD r0 r9 r2 LDREQD r8 abc4 Incorrect examples LDRD r1 r6 Rd must be even STRD r14 r9 36 Rd must not be r14 STRD r2 r3 r6 Rn must not be Rd or R d 1 ...

Page 128: ... ascending stack Rn is the base register the ARM register containing the initial address for the transfer Rn must not be r15 is an optional suffix If is present the final address is written back into Rn reglist is a list of registers to be loaded or stored enclosed in braces It can contain register ranges It must be comma separated if it contains more than one register or register range see Exampl...

Page 129: ...e register with writeback If Rn is in reglist and writeback is specified with the suffix if op is STM and Rn is the lowest numbered register in reglist the initial value of Rn is stored otherwise the loaded or stored value of Rn is unpredictable Architectures These instructions are available in all versions of the ARM architecture In T variants of ARM architecture v5 and above a load to r15 causes...

Page 130: ...he offset is subtracted from Rn Otherwise the offset is added to Rn expr is an expression evaluating to an integer in the range 4095 to 4095 This is often a numeric constant Rm is a register containing a value to be used as the offset shift is an optional shift to be applied to Rm It can be any one of ASR n arithmetic shift right n bits 1 n 32 LSL n logical shift left n bits 0 n 31 LSR n logical s...

Page 131: ...is to speed up later memory accesses Alignment There are no alignment restrictions on the address If a system control coprocessor cp15 is present then it will not generate an alignment exception for any PLD instruction Architectures This instruction is available in E variants of ARM architecture v5 and above Examples PLD r2 PLD r15 280 PLD r9 2481 PLD r0 av 4 av 4 must evaluate at assembly time to...

Page 132: ...d into Rd Rm is an ARM register The contents of Rm is saved to memory Rm can be the same register as Rd In this case the contents of the register is swapped with the contents of the memory location Rn is an ARM register The contents of Rn specify the address in memory with which data is to be swapped Rn must be a different register from both Rd and Rm Non word aligned addresses Non word aligned ad...

Page 133: ...ible second operand on page 4 24 ADD SUB RSB ADC SBC and RSC on page 4 27 Add subtract and reverse subtract each with or without carry AND ORR EOR and BIC on page 4 30 Logical AND OR Exclusive OR and Bit Clear MOV and MVN on page 4 32 Move and Move Not CMP and CMN on page 4 34 Compare and Compare Negative TST and TEQ on page 4 36 Test and Test Equivalence CLZ on page 4 38 Count Leading Zeroes ...

Page 134: ...a 32 bit word but see Instruction substitution on page 4 26 Rm is the ARM register holding the data for the second operand The bit pattern in the register can be shifted or rotated in various ways shift is an optional shift to be applied to Rm It can be any one of ASR n arithmetic shift right n bits 1 n 32 LSL n logical shift left n bits 0 n 31 LSR n logical shift right n bits 1 n 32 ROR n rotate ...

Page 135: ... 0 Logical shift left by n bits multiplies the value contained in Rm by 2n if the contents are regarded as an unsigned integer Overflow may occur without warning The right hand n bits of the register are set to 0 ROR Rotate right by n bits moves the right hand n bits of the register into the left hand n bits of the result At the same time all other bits are moved right by n bits see Figure 4 1 Fig...

Page 136: ..._8r cannot be expressed as a rotated 8 bit pattern but its logical inverse or negation could be the assembler substitutes the other instruction of the pair and inverts or negates immed_8r Be aware of this when comparing disassembly listings with source code Examples ADD r3 r7 1020 immed_8r 1020 is 0xFF rotated right by 30 bits AND r0 r5 r2 r2 contains the data for Operand2 SUB r11 r12 r3 ASR 5 Ope...

Page 137: ... Operand2 The SUB instruction subtracts the value of Operand2 from the value in Rn The RSB Reverse SuBtract instruction subtracts the value in Rn from the value of Operand2 This is useful because of the wide range of options for Operand2 ADC SBC and RSC are used to synthesize multiword arithmetic see Multiword arithmetic examples on page 4 28 The ADC ADd with Carry instruction adds the values in R...

Page 138: ...mode The effect of such an instruction is unpredictable but the assembler cannot warn you at assembly time You cannot use r15 for Rd or any operand in any data processing instruction that has a register controlled shift see Flexible second operand on page 4 24 Architectures These instructions are available in all versions of the ARM architecture Examples ADD r2 r1 r3 SUBS r8 r6 240 sets the flags ...

Page 139: ...DC r5 r1 r3 adding the most significant words These instructions subtract one 96 bit integer from another SUBS r3 r6 r9 SBCS r4 r7 r10 SBC r5 r8 r11 For clarity the above examples use consecutive registers for multiword values There is no requirement to do this The following for example is perfectly valid SUBS r6 r6 r9 SBCS r9 r2 r1 SBC r2 r8 r11 ...

Page 140: ...le second operand See Flexible second operand on page 4 24 for details of the options Usage The AND EOR and ORR instructions perform bitwise AND Exclusive OR and OR operations on the values in Rn and Operand2 The BIC BIt Clear instruction performs an AND operation on the bits in Rn with the complements of the corresponding bits in the value of Operand2 In certain circumstances the assembler can su...

Page 141: ... chapter in ADS Developer Guide Caution Do not use the S suffix when using r15 as Rd in User mode or System mode The effect of such an instruction is unpredictable but the assembler cannot warn you at assembly time You cannot use r15 for Rd or any operand in any data processing instruction that has a register controlled shift see Flexible second operand on page 4 24 Architectures These instruction...

Page 142: ... operand See Flexible second operand on page 4 24 for details of the options Usage The MOV instruction copies the value of Operand2 into Rd The MVN instruction takes the value of Operand2 performs a bitwise logical NOT operation on the value and places the result into Rd In certain circumstances the assembler can substitute MVN for MOV or MOV for MVN Be aware of this when reading disassembly listi...

Page 143: ...sor Exceptions chapter in ADS Developer Guide Caution Do not use the S suffix when using r15 as Rd in User mode or System mode The effect of such an instruction is unpredictable but the assembler cannot warn you at assembly time You cannot use r15 for Rd or any operand in any data processing instruction that has a register controlled shift see Flexible second operand on page 4 24 Architectures The...

Page 144: ...MP instruction subtracts the value of Operand2 from the value in Rn This is the same as a SUBS instruction except that the result is discarded The CMN instruction adds the value of Operand2 to the value in Rn This is the same as an ADDS instruction except that the result is discarded In certain circumstances the assembler can substitute CMN for CMP or CMP for CMN Be aware of this when reading disa...

Page 145: ...01 ARM Limited All rights reserved 4 35 Architectures These instructions are available in all versions of the ARM architecture Examples CMP r2 r9 CMN r0 6400 CMPGT r13 r7 LSL 2 Incorrect example CMP r2 r15 ASR r0 r15 not allowed with register controlled shift ...

Page 146: ...ST instruction performs a bitwise AND operation on the value in Rn and the value of Operand2 This is the same as a ANDS instruction except that the result is discarded The TEQ instruction performs a bitwise Exclusive OR operation on the value in Rn and the value of Operand2 This is the same as a EORS instruction except that the result is discarded Condition flags These instructions update the N an...

Page 147: ... ARM Limited All rights reserved 4 37 Architectures These instructions are available in all versions of the ARM architecture Examples TST r0 0x3F8 TEQEQ r10 r9 TSTNE r1 r5 ASR r1 Incorrect example TEQ r15 r1 ROR r0 r15 not allowed with register controlled shift ...

Page 148: ...register for the result Rd must not be r15 Rm is the operand register Usage The CLZ instruction counts the number of leading zeroes in the value in Rm and returns the result in Rd The result value is 32 if no bits are set in the source register and zero if bit 31 is set Condition flags This instruction does not affect the flags Architectures This instruction is available in ARM architecture versio...

Page 149: ...y 16 bit by 16 bit 32 bit result SMLAxy on page 4 46 Signed multiply accumulate 16 bit by 16 bit 32 bit accumulate SMULWy on page 4 48 Signed multiply 32 bit by 16 bit top 32 bit result SMLAWy on page 4 49 Signed multiply accumulate 32 bit by 16 bit top 32 bit accumulate SMLALxy on page 4 51 Signed multiply accumulate 16 bit by 16 bit 64 bit accumulate MIA MIAPH and MIAxy on page 4 53 XScale copro...

Page 150: ...m Rs Rn are ARM registers holding the operands r15 cannot be used for any of Rd Rm Rs or Rn Rd cannot be the same as Rm Usage The MUL instruction multiplies the values from Rm and Rs and places the least significant 32 bits of the result in Rd The MLA instruction multiplies the values from Rm and Rs adds the value from Rn and places the least significant 32 bits of the result in Rd Condition flags...

Page 151: ...Copyright 2000 2001 ARM Limited All rights reserved 4 41 Examples MUL r10 r2 r5 MLA r10 r2 r1 r5 MULS r0 r2 r2 MULLT r2 r3 r2 MLAVCS r8 r6 r3 r8 Incorrect examples MUL r15 r0 r3 use of r15 not allowed MLA r1 r1 r6 Rd cannot be the same as Rm ...

Page 152: ...Rs RdLo RdHi and Rm must all be different registers Usage The UMULL instruction interprets the values from Rm and Rs as unsigned integers It multiplies these integers and places the least significant 32 bits of the result in RdLo and the most significant 32 bits of the result in RdHi The UMLAL instruction interprets the values from Rm and Rs as unsigned integers It multiplies these integers and ad...

Page 153: ... earlier do not affect the C or V flags in ARM architecture v5 and later Architectures These instructions are available in ARM architecture v3M and ARM architecture v4 and above except xM variants Examples UMULL r0 r4 r5 r6 UMLALS r4 r5 r3 r8 SMLALLES r8 r9 r7 r6 SMULLNE r0 r1 r9 r0 Rs can be the same as other registers Incorrect examples UMULL r1 r15 r10 r2 use of r15 not allowed SMULLLE r0 r1 r0...

Page 154: ...Rs cond is an optional condition code see Conditional execution on page 4 4 Rd is the ARM register for the result Rm Rs are the ARM registers holding the values to be multiplied r15 cannot be used for any of Rd Rm or Rs Any combination of Rd Rm and Rs can use the same registers Usage The SMULxy instruction multiplies the 16 bit signed integers from the selected halves of Rm and Rs and places the 3...

Page 155: ...ARM Instruction Reference ARM DUI 0068B Copyright 2000 2001 ARM Limited All rights reserved 4 45 Incorrect examples SMULBT r15 r2 r0 use of r15 not allowed SMULTTS r0 r6 r2 use of S suffix not allowed ...

Page 156: ...sult Rm Rs are the ARM registers holding the values to be multiplied Rn is the ARM register holding the value to be added r15 cannot be used for any of Rd Rm Rs or Rn Any combination of Rd Rm Rs and Rn can use the same registers Usage The SMLAxy instruction multiplies the 16 bit signed integers from the selected halves of Rm and Rs adds the 32 bit result to the 32 bit value in Rn and places the re...

Page 157: ...reserved 4 47 Architectures This instruction is available in all E variants of ARM architecture v5 and above Examples SMLATT r8 r1 r0 r8 SMLABBNE r0 r2 r1 r10 SMLABT r0 r0 r3 r5 Incorrect examples SMLATB r0 r7 r8 r15 use of r15 not allowed SMLATTS r0 r6 r2 use of S suffix not allowed ...

Page 158: ...are the ARM registers holding the operands r15 cannot be used for any of Rd Rm or Rs Any combination of Rd Rm and Rs can use the same registers Usage The SMULWy instruction multiplies the signed integer from the selected half of Rs by the signed integer from Rm and places the upper 32 bits of the 48 bit result in Rd Condition flags This instruction does not affect any flags Architectures This inst...

Page 159: ...e multiplied Rn is the ARM register holding the value to be added r15 cannot be used for any of Rd Rm Rs or Rn Any combination of Rd Rm Rs and Rn can use the same registers Usage The SMLAWy instruction multiplies the signed integer from the selected half of Rs by the signed integer from Rm adds the 32 bit result to the 32 bit value in Rn and places the result in Rd Condition flags This instruction...

Page 160: ...reserved ARM DUI 0068B Architectures This instruction is available in all E variants of ARM architecture v5 and above Examples SMLAWB r2 r4 r7 r1 SMLAWTVS r0 r0 r9 r2 Incorrect examples SMLAWT r15 r9 r3 r1 use of r15 not allowed SMLAWBS r0 r4 r5 r1 use of S suffix not allowed ...

Page 161: ...egisters for the result They also hold the add in value Rm Rs are the ARM registers holding the values to be multiplied r15 cannot be used for any of RdHi RdLo Rm or Rs Any combination of RdHi RdLo Rm or Rs can use the same registers Usage The SMLALxy instruction multiplies the signed integer from the selected half of Rs by the signed integer from the selected half of Rm and adds the 32 bit result...

Page 162: ...2 Copyright 2000 2001 ARM Limited All rights reserved ARM DUI 0068B Examples SMLALTB r2 r3 r7 r1 SMLALBTVS r0 r1 r9 r2 Incorrect examples SMLALTT r8 r9 r3 r15 use of r15 not allowed SMLALBBS r0 r1 r5 r2 use of S suffix not allowed ...

Page 163: ... standard name is accx where x is an integer in the range 0 n The value of n depends on the processor It is 0 in current processors Rm Rs are the ARM registers holding the values to be multiplied x is either B or T B means use the bottom end bits 15 0 of Rm T means use the top end bits 31 16 of Rm y is either B or T B means use the bottom end bits 15 0 of Rs T means use the top end bits 31 16 of R...

Page 164: ...sult to the 40 bit value in Acc Condition flags These instructions do not affect any flags Note These instructions cannot raise an exception If overflow occurs on these instructions the result wraps round without any warning Architectures These instructions are only available in XScale Examples MIA acc0 r5 r0 MIALE acc0 r1 r9 MIAPH acc0 r0 r7 MIAPHNE acc0 r11 r10 MIABB acc0 r8 r9 MIABT acc0 r8 r8 ...

Page 165: ...Rm Rn where op is one of QADD QSUB QDADD or QDSUB cond is an optional condition code see Conditional execution on page 4 4 Rd is the ARM register for the result Rm Rn are the ARM registers holding the operands r15 cannot be used for any of Rd Rm or Rn Usage The QADD instruction adds the values in Rm and Rn The QSUB instruction subtracts the value in Rn from the value in Rm The QDADD instruction ca...

Page 166: ...curs they set the Q flag To read the state of the Q flag use an MRS instruction see MRS on page 4 73 Note These instructions never clear the Q flag even if saturation does not occur To clear the Q flag use an MSR instruction see MSR on page 4 74 Architectures These instructions are available in E variants of ARM architecture v5 and above Examples QADD r0 r1 r9 QDSUBLT r9 r0 r1 Examples QSUBS r3 r4...

Page 167: ...ted All rights reserved 4 57 4 6 ARM branch instructions This section contains the following subsections B and BL on page 4 58 Branch and Branch with Link BX on page 4 59 Branch and exchange instruction set BLX on page 4 60 Branch with Link and exchange instruction set ...

Page 168: ... BL instruction copies the address of the next instruction into r14 lr the link register and causes a branch to label Machine level B and BL instructions have a range of 32Mb from the address of the current instruction However you can use these instructions even if label is out of range Often you do not know where label is placed by the linker When necessary the ARM linker adds code to allow longe...

Page 169: ... branch to Bit 0 of Rm is not used as part of the address If bit 0 of Rm is set the instruction sets the T flag in the CPSR and the code at the destination is interpreted as Thumb code If bit 0 of Rm is clear bit 1 must not be set Usage The BX instruction causes a branch to the address held in Rm and changes instruction set to Thumb if bit 0 of Rm is set Architectures This instruction is available...

Page 170: ...d the code at the destination is interpreted as Thumb code If bit 0 of Rm is clear bit 1 must not be set label is a program relative expression See Register relative and program relative expressions on page 3 23 for more information Note BLX label cannot be conditional BLX label always causes a change to Thumb state Usage The BLX instruction copies the address of the next instruction into r14 lr t...

Page 171: ...ght 2000 2001 ARM Limited All rights reserved 4 61 Architectures This instruction is available in all T variants of ARM architecture v5 and above Examples BLX r2 BLXNE r0 BLX thumbsub Incorrect example BLXMI thumbsub BLX label cannot be conditional ...

Page 172: ...t contains the following sections CDP CDP2 on page 4 63 Coprocessor data operations MCR MCR2 MCRR on page 4 64 Move to coprocessor from ARM registers possibly with coprocessor operations MRC MRC2 on page 4 65 Move to ARM register from coprocessor possibly with coprocessor operations MRRC on page 4 66 Move to two ARM registers from coprocessor possibly with coprocessor operations LDC STC on page 4 ...

Page 173: ...s the name of the coprocessor the instruction is for The standard name is pn where n is an integer in the range 0 15 opcode1 is a coprocessor specific opcode CRd CRn CRm are coprocessor registers opcode2 is an optional coprocessor specific opcode Usage The use of these instructions depends on the coprocessor See the coprocessor documentation for details Note CDP2 is always unconditional Architectu...

Page 174: ...is the name of the coprocessor the instruction is for The standard name is pn where n is an integer in the range 0 15 opcode1 is a coprocessor specific opcode Rd Rn are ARM source registers They must not be r15 CRn CRm are coprocessor registers opcode2 is an optional coprocessor specific opcode Usage The use of these instructions depends on the coprocessor See the coprocessor documentation for det...

Page 175: ...4 coproc is the name of the coprocessor the instruction is for The standard name is pn where n is an integer in the range 0 15 opcode1 is a coprocessor specific opcode Rd is the ARM destination register If Rd is r15 only the flags field is affected CRn CRm are coprocessor registers opcode2 is an optional coprocessor specific opcode Usage The use of these instructions depends on the coprocessor See...

Page 176: ...de see Conditional execution on page 4 4 coproc is the name of the coprocessor the instruction is for The standard name is pn where n is an integer in the range 0 15 opcode is a coprocessor specific opcode Rd Rn are ARM destination registers You cannot use r15 for Rd or Rn CRm is the coprocessor source register Usage The use of this instruction depends on the coprocessor See the coprocessor docume...

Page 177: ...specifying a long transfer coproc is the name of the coprocessor the instruction is for The standard name is pn where n is an integer in the range 0 15 CRd is the coprocessor register to load or save Rn is the register on which the memory address is based If r15 is specified the value used is the address of the current instruction plus eight is an optional minus sign If is present the offset is su...

Page 179: ... is for The standard name is pn where n is an integer in the range 0 15 CRd is the coprocessor register to load or save Rn is the register on which the memory address is based If r15 is specified the value used is the address of the current instruction plus eight is an optional minus sign If is present the offset is subtracted from Rn Otherwise the offset is added to Rn offset is an expression eva...

Page 181: ...tware interrupt MRS on page 4 73 Move the contents of the CPSR or SPSR to a general purpose register MSR on page 4 74 Load specified fields of the CPSR or SPSR with an immediate constant or from the contents of a general purpose register BKPT on page 4 76 Breakpoint MAR MRA on page 4 77 XScale coprocessor 0 instructions Transfer between two general purpose registers and a 40 bit internal accumulat...

Page 182: ...n integer in the range 0 224 1 a 24 bit integer Usage The SWI instruction causes a SWI exception This means that the processor mode changes to Supervisor the CPSR is saved to the Supervisor mode SPSR and execution branches to the SWI vector see the Handling Processor Exceptions chapter in ADS Developer Guide Condition flags This instruction does not affect the flags Architectures This instruction ...

Page 183: ...PSR Usage Use MRS in combination with MSR as part of a read modify write sequence for updating a PSR for example to change processor mode or to clear the Q flag Caution You must not attempt to access the SPSR when the processor is in User or System mode This is your responsibility The assembler cannot warn you about this as it does not know what processor mode code will be executed in Condition fl...

Page 184: ...s specifies the field or fields to be moved fields can be one or more of c control field mask byte PSR 7 0 x extension field mask byte PSR 15 8 s status field mask byte PSR 23 16 f flags field mask byte PSR 31 24 immed_8r is an expression evaluating to a numeric constant The constant must correspond to an 8 bit pattern rotated by an even number of bits within a 32 bit word Rm is the source registe...

Page 186: ... bit integer immed_16 is ignored by ARM hardware but can be used by a debugger to store additional information about the breakpoint Usage The BKPT instruction causes the processor to enter Debug mode Debug tools can use this to investigate system state when the instruction at a particular address is reached Architectures This instruction is available in ARM architecture versions 5 and above Exampl...

Page 187: ... standard name is accx where x is an integer in the range 0 n The value of n depends on the processor It is 0 for current processors RdLo RdHi are general purpose registers Usage The MAR instruction copies the contents of RdLo to bits 31 0 of Acc and the least significant byte of RdHi to bits 39 32 of Acc The MRA instruction copies bits 31 0 of Acc to RdLo copies bits 39 32 of Acc to RdHi sign ext...

Page 188: ...ctions available in ARM state are described in the following sections ADR ARM pseudo instruction on page 4 79 Load a program relative or register relative address short range ADRL ARM pseudo instruction on page 4 80 Load a program relative or register relative address into a register medium range LDR ARM pseudo instruction on page 4 82 Load a register with a 32 bit constant value or an address unl...

Page 189: ...ion or the base register see Register relative and program relative expressions on page 3 23 Note For program relative expressions the given range is relative to a point two words after the address of the current instruction Usage ADR always assembles to one instruction The assembler attempts to produce a single ADD or SUB instruction to load the address If the address cannot be constructed in a s...

Page 190: ...KB More distant addresses can be used if the alignment is 16 bytes or more The address can be either before or after the address of the instruction or the base register see Register relative and program relative expressions on page 3 23 Note For program relative expressions the given range is relative to a point two words after the address of the current instruction Usage ADRL always assembles to ...

Page 191: ...ted All rights reserved 4 81 If expr is program relative it must evaluate to an address in the same code section as the ADRL pseudo instruction Otherwise it might be out of range after linking Example start MOV r0 10 ADRL r4 start 60000 ADD r4 pc 0xe800 ADD r4 r4 0x254 ...

Page 192: ...embler generates a MOV or MVN instruction if the value of expr is within range if the value of expr is not within range of a MOV or MVN instruction the assembler places the constant in a literal pool and generates a program relative LDR instruction that reads the constant from the literal pool label expr is a program relative or external expression The assembler places the value of label expr in a...

Page 193: ...LDR Note An address loaded in this way is fixed at link time so the code is not position independent The offset from the PC to the value in the literal pool must be less than 4KB You are responsible for ensuring that there is a literal pool within range See LTORG on page 7 14 for more information See Loading constants into registers on page 2 25 for a more detailed explanation of how to use LDR an...

Page 194: ...struction NOP generates the preferred ARM no operation code The following instruction might be used but this is not guaranteed MOV r0 r0 Syntax NOP Usage NOP cannot be used conditionally Not executing a no operation is the same as executing it so conditional execution is not required ALU status flags are unaltered by NOP ...

Page 195: ... ARM C and C compilers It contains the following sections Thumb memory access instructions on page 5 4 Thumb arithmetic instructions on page 5 15 Thumb general data processing instructions on page 5 22 Thumb branch instructions on page 5 31 Thumb software interrupt and breakpoint instructions on page 5 37 Thumb pseudo instructions on page 5 39 See Table 5 1 on page 5 2 to locate individual directi...

Page 196: ...k and exchange instruction sets page 5 36 5T BX Branch and exchange instruction sets page 5 35 4T CMN CMP Compare negative Compare page 5 26 4T EOR Logical exclusive OR page 5 23 4T LDMIA Load multiple registers increment after page 5 13 4T LDR Load register immediate offset page 5 5 4T LDR Load register register offset page 5 7 4T LDR Load register pc or sp relative page 5 9 4T LDR Load register ...

Page 197: ...Store register immediate offset page 5 5 4T STR Store register register offset page 5 7 4T STR Store register pc or sp relative page 5 9 4T SUB Subtract page 5 15 4T SWI Software interrupt page 5 37 4T TST Test bits page 5 30 4T a nT available in T variants of ARM architecture version n and above Table 5 1 Location of Thumb instructions and pseudo instructions continued Instruction mnemonic Brief ...

Page 198: ... a register LDR and STR register offset on page 5 7 Load Register and Store Register Address in memory specified as a register based offset from a value in a register LDR and STR pc or sp relative on page 5 9 Load Register and Store Register Address in memory specified as an immediate offset from a value in the pc or the sp PUSH and POP on page 5 11 Push low registers and optionally the LR onto th...

Page 199: ...ecifying an unsigned byte transfer Rd is the register to be loaded or stored Rd must be in the range r0 r7 Rn is the register containing the base address Rn must be in the range r0 r7 immed_5xN is the offset It is an expression evaluating at assembly time to a multiple of N in the range 0 31N Usage STR instructions store a word halfword or byte to memory LDR instructions load a word halfword or by...

Page 200: ...system coprocessor cp15 or alignment checking is disabled A non aligned load corrupts Rd A non aligned save corrupts two or four bytes in memory The corrupted location in memory is address AND NOT 0x1 for halfword saves and address AND NOT 0x3 for word saves Architectures These instructions are available in all T variants of the ARM architecture Examples LDR r3 r5 0 STRB r0 r3 31 STRH r7 r3 16 LDR...

Page 201: ...e register byte Note There is no distinction between signed and unsigned store instructions Rd is the register to be loaded or stored Rd must be in the range r0 r7 Rn is the register containing the base address Rn must be in the range r0 r7 Rm is the register containing the offset Rm must be in the range r0 r7 Usage STR instructions store a word halfword or byte from Rd to memory LDR instructions ...

Page 202: ...alignment checking is enabled If your system does not have a system coprocessor cp15 or alignment checking is disabled A non aligned load corrupts Rd A non aligned save corrupts memory The corrupted location in memory is the halfword at address AND NOT 0x1 for halfword saves and the word at address AND NOT b11 for word saves Architectures These instructions are available in all T variants of the A...

Page 203: ... time to a multiple of 4 in the range 0 to 1020 label is a program relative expression See Register relative and program relative expressions on page 3 23 for more information label must be after the current instruction and within 1KB of it Usage STR instructions store a word to memory LDR instructions load a word from memory The address is found by adding the offset to the base address from pc or...

Page 204: ...is address AND NOT b11 Architectures These instructions are available in all T variants of the ARM architecture Examples LDR r2 pc 1016 LDR r5 localdata LDR r0 sp 920 STR r1 sp 20 Incorrect examples LDR r13 pc 8 Rd must be in range r0 r7 STR r7 pc 64 there is no pc relative STR instruction STRH r0 sp 16 there are no pc or sp relative halfword or byte transfers LDR r2 pc 81 immediate must be a mult...

Page 205: ... where reglist is a comma separated list of low registers or low register ranges Note The braces in the syntax description are part of the instruction format They do not indicate that the register list is optional There must be at least one register in the list Usage Thumb stacks are full descending stacks The stack grows downwards and the sp points to the last entry on the stack Registers are sto...

Page 206: ...o ARM state bits 1 0 must not have the value b10 In ARM architecture version 4T and earlier bits 1 0 of the value loaded to the pc are ignored so POP cannot be used to change state Condition flags These instructions do not affect the flags Architectures These instructions are available in all T variants of the ARM architecture Examples PUSH r0 r3 r5 PUSH r1 r4 r7 pushes r1 r4 r5 r6 and r7 PUSH r0 ...

Page 207: ...e instruction format They do not indicate that the register list is optional There must be at least one register in the list Usage Registers are loaded stored and in numerical order with the lowest numbered register at the address initially in Rn The value in Rn is incremented by 4 times the number of registers in reglist If Rn is in reglist for an LDMIA instruction the final value of Rn is the va...

Page 208: ...All rights reserved ARM DUI 0068B Examples LDMIA r3 r0 r4 LDMIA r5 r0 r7 STMIA r0 r6 r7 STMIA r3 r3 r5 r7 Incorrect examples LDMIA r3 r0 r9 high registers not allowed STMIA r5 must be at least one register in list STMIA r5 r1 r6 value stored from r5 is unpredictable ...

Page 209: ...e 5 16 Add and subtract ADD high or low registers on page 5 18 Add values in registers one or both of them in the range r8 to r15 ADD and SUB sp on page 5 19 Increment or decrement sp by an immediate constant ADD pc or sp relative on page 5 20 Add an immediate constant to the value from sp or pc and place the result into a low register ADC SBC and MUL on page 5 21 Add with carry Subtract with carr...

Page 210: ...to the same register Syntax op Rd Rn Rm op Rd Rn expr3 op Rd expr8 where op is either ADD or SUB Rd is the destination register It is also used for the first operand in op Rd expr8 instructions Rn is a register containing the first operand Rm is a register containing the second operand expr3 is an expression evaluating at assembly time to an integer in the range 7 to 7 expr8 is an expression evalu...

Page 211: ...Be aware of this when looking at disassembly listings Restrictions Rd Rn and Rm must all be low registers that is in the range r0 to r7 Condition flags These instructions update the N Z C and V flags Architectures These instructions are available in all T variants of the ARM architecture Examples ADD r3 r1 r5 SUB r0 r4 5 ADD r7 201 ADD r1 vc 4 vc 4 must evaluate at assembly time to an integer in t...

Page 212: ...on adds the values in Rd and Rm and places the result in Rd Note An ADD Rd Rm instruction where both Rd and Rm are low registers assembles to an ADD Rd Rd Rm instruction see ADD and SUB low registers on page 5 16 Be aware of this when looking at disassembly listings Condition flags The N Z C and V condition flags are updated if both Rd and Rm are low registers unaffected otherwise Architectures Th...

Page 213: ...he result in Rd Note An ADD instruction with a negative value for expr assembles to the corresponding SUB instruction with a positive constant A SUB instruction with a negative value for expr assembles to the corresponding ADD instruction with a positive constant Be aware of this when looking at disassembly listings Condition flags This instruction does not affect the flags Architectures This inst...

Page 214: ...xpression that evaluates at assembly time to a multiple of 4 in the range 0 1020 Usage This instruction adds the value of expr to the value from Rp and places the result in Rd Note If Rp is the pc the value used is the address of the current instruction 4 AND FFFFFFFC Condition flags This instruction does not affect the flags Architectures This instruction is available in all T variants of the ARM...

Page 215: ...word addition SBC subtracts the value in Rm from the value in Rd taking account of the carry flag and places the result in Rd Use this to synthesize multiword subtraction MUL multiplies the values in Rd and Rm and places the result in Rd Restrictions Rd and Rm must be low registers that is in the range r0 to r7 Condition flags ADC and SBC update the N Z C and V flags MUL updates the N and Z flags ...

Page 216: ...ocessing instructions This section contains the following subsections AND ORR EOR and BIC on page 5 23 Bitwise logical operations ASR LSL LSR and ROR on page 5 24 Shift and rotate operations CMP and CMN on page 5 26 Compare and Compare Negative MOV MVN and NEG on page 5 28 Move Move NOT and Negate TST on page 5 30 Test bits ...

Page 217: ...These instructions perform a bitwise logical operation on the contents of Rd and Rm and place the result in Rd The operations are as follows the AND instruction performs a logical AND operation the ORR instruction performs a logical OR operation the EOR instruction performs a logical Exclusive OR operation the BIC instruction performs an Rd AND NOT Rm operation Condition flags These instructions u...

Page 218: ...ed LSR Logical Shift Right Vacated bits are cleared ROR Rotate Right Bits moved out of the right hand end of the register are rotated back into the left hand end Note ROR can only be used with a register controlled shift Rd is the destination register It is also the source register for register controlled shifts Rd must be in the range r0 r7 Rs is the register containing the shift value for regist...

Page 219: ...y the shift to it and place the result into Rd Condition flags These instructions update the N and Z flags according to the result The V flag is not affected The C flag is unaffected if the shift value is zero otherwise contains the last bit shifted out of the source register Architectures These instructions are available in all T variants of the ARM architecture Examples ASR r3 r5 LSR r0 r2 6 LSR...

Page 220: ... operand Usage These instructions update the condition flags but do not place a result in a register The CMP instruction subtracts the value of expr or the value in Rm from the value in Rn The CMN instruction adds the values in Rm and Rn Restrictions In CMP Rn expr and CMN instructions Rn and Rm must be in the range r0 to r7 In CMP Rn Rm instructions Rn and Rm can be any register r0 to r15 Conditi...

Page 221: ...M Limited All rights reserved 5 27 Examples CMP r2 255 CMP r7 r12 high register IS allowed with CMP Rn Rm CMN r1 r5 Incorrect examples CMP r2 508 immediate value out of range CMP r9 24 high register not allowed with expr CMN r0 r10 high register not allowed with CMN ...

Page 222: ...ange 0 255 Rm is the source register Usage The MOV instruction places expr or the value from Rm in Rd The MVN instruction takes the value in Rm performs a bitwise logical NOT operation on the value and places the result in Rd The NEG instruction takes the value in Rm multiplies it by 1 and places the result in Rd Restrictions In MOV Rd expr MVN and NEG instructions Rd and Rm must be in the range r...

Page 223: ...isters r0 r7 the N and Z flags are updated and C and V flags are cleared Note You can use LSL with a shift of zero to move between low registers without clearing the C and V flags see ASR LSL LSR and ROR on page 5 24 Architectures These instructions are available in all T variants of the ARM architecture Examples MOV r3 0 MOV r0 r12 does not update flags MVN r7 r1 NEG r2 r2 Incorrect examples MOV ...

Page 224: ...and Usage This instruction performs a bitwise logical AND operation on the values in Rm and Rn It updates the condition flags but does not place a result in a register Restrictions Rn and Rm must be in the range r0 r7 Condition flags This instruction updates the N and Z flags according to the result The C and V flags are unaffected Architectures This instruction is available in all T variants of t...

Page 225: ...d All rights reserved 5 31 5 4 Thumb branch instructions This section contains the following subsections B on page 5 32 Branch BL on page 5 34 Branch with Link BX on page 5 35 Branch and exchange instruction set BLX on page 5 36 Branch with Link and exchange instruction set ...

Page 226: ...ithin the same piece of code See Register relative and program relative expressions on page 3 23 for more information label must be within 252 to 258 bytes of the current instruction if cond is used 2KB if the instruction is unconditional Usage The B instruction causes a branch to label if cond is satisfied or if cond is not used Note label must be within the specified limits The ARM linker cannot...

Page 227: ...l NE Z clear Not equal CS HS C set Higher or same unsigned CC LO C clear Lower unsigned MI N set Negative PL N clear Positive or zero VS V set Overflow VC V clear No overflow HI C set and Z clear Higher unsigned LS C clear or Z set Lower or same unsigned GE N and V the same Signed LT N and V different Signed GT Z clear and N and V the same Signed LE Z set or N and V different Signed ...

Page 228: ...rmation Usage The BL instruction copies the address of the next instruction into r14 lr the link register and causes a branch to label The machine level instruction cannot branch to an address outside 4Mb of the current instruction When necessary the ARM linker inserts code a veneer to allow longer branches see The ARM linker chapter in ADS Linker and Utilities Guide Architectures This instruction...

Page 229: ...to Bit 0 of Rm is not used as part of the address If bit 0 of Rm is clear bit 1 must also be clear the instruction clears the T flag in the CPSR and the code at the destination is interpreted as ARM code Usage The BX instruction causes a branch to the address held in Rm and changes instruction set to Thumb if bit 0 of Rm is set Architectures This instruction is available in all T variants of the A...

Page 230: ...program relative expressions on page 3 23 for more information BLX label always causes a change to ARM state Usage The BLX instruction copies the address of the next instruction into r14 lr the link register causes a branch to label or to the address held in Rm changes instruction set to ARM if either bit 0 of Rm is clear the BLX label form is used The machine level instruction cannot branch to an...

Page 231: ...eption This means that the processor state changes to ARM the processor mode changes to Supervisor the CPSR is saved to the Supervisor Mode SPSR and execution branches to the SWI vector see the Handling Processor Exceptions chapter in ADS Developer Guide immed_8 is ignored by the processor However it is present in bits 7 0 of the instruction opcode It can be retrieved by the exception handler to d...

Page 232: ...s the processor to enter Debug mode Debug tools can use this to investigate system state when the instruction at a particular address is reached immed_8 is ignored by the processor However it is present in bits 7 0 of the instruction opcode It can be used by a debugger to store additional information about the breakpoint Architectures This instruction is available in T variants of ARM architecture...

Page 233: ...mbler supports a number of Thumb pseudo instructions that are translated into the appropriate Thumb instructions at assembly time The pseudo instructions that are available in Thumb state are in the following sections ADR Thumb pseudo instruction on page 5 40 LDR Thumb pseudo instruction on page 5 41 NOP Thumb pseudo instruction on page 5 43 ...

Page 234: ...sion The offset must be positive and less than 1KB expr must be defined locally it cannot be imported Usage In Thumb state ADR can generate word aligned addresses only Use the ALIGN directive to ensure that expr is aligned see ALIGN on page 7 50 expr must evaluate to an address in the same code section as the ADR pseudo instruction There is no guarantee that the address will be within range after ...

Page 235: ...al pool and generates a program relative LDR instruction that reads the constant from the literal pool label exp is a program relative or external expression The assembler places the value of label exp in a literal pool and generates a program relative LDR instruction that loads the value from the literal pool If label exp is an external expression or is not contained in the current section the as...

Page 236: ...served ARM DUI 0068B To load a program relative or external address into a register The address remains valid regardless of where the linker places the ELF section containing the LDR Example LDR r1 0xfff loads 0xfff into r1 LDR r2 labelname loads the address of labelname into r2 ...

Page 237: ... rights reserved 5 43 5 6 3 NOP Thumb pseudo instruction NOP generates the preferred Thumb no operation instruction The following instruction might be used but this is not guaranteed MOV r8 r8 Syntax The syntax for NOP is NOP Condition flags ALU status flags are unaltered by NOP ...

Page 239: ...the following sections The vector floating point coprocessor on page 6 4 Floating point registers on page 6 5 Vector and scalar operations on page 6 7 VFP and condition codes on page 6 8 VFP system registers on page 6 10 Flush to zero mode on page 6 13 VFP instructions on page 6 15 VFP pseudo instruction on page 6 38 VFP directives and vector notation on page 6 40 See Table 6 1 on page 6 2 for loc...

Page 240: ...egister to half of double precision page 6 30 Scalar All FMDRR Transfer from two ARM registers to double precision page 6 29 Scalar VFPv2 FMRDH FMRDL Transfer from half of double precision to ARM register page 6 30 Scalar All FMRRD Transfer from double precision to two ARM registers page 6 29 Scalar VFPv2 FMRRS Transfer between two ARM registers and two single precision page 6 32 Scalar VFPv2 FMRS...

Page 241: ...ll FSITO Convert signed integer to floating point page 6 35 Scalar All FSQRT Square Root page 6 36 Vector All FST Store page 6 23 Scalar All FSTM Store multiple page 6 25 All FSUB Subtract page 6 18 Vector All FTOSI FTOUI Convert floating point to signed or unsigned integer page 6 37 Scalar All FUITO Convert unsigned integer to floating point page 6 35 Scalar All Table 6 1 Location of descriptions...

Page 242: ...hort vectors of up to eight single precision or four double precision numbers are handled particularly efficiently Most arithmetic instructions can be used on these vectors allowing single instruction multiple data SIMD parallelism In addition the floating point load and store instructions have multiple register forms allowing vectors to be transferred to and from memory efficiently For further de...

Page 243: ...double precision values the same registers for single precision values and double precision values at different times Do not attempt to use corresponding single precision and double precision registers at the same time No damage is caused but the results are meaningless 6 2 1 Register banks The VFP registers are arranged as four banks of eight single precision registers s0 to s7 s8 to s15 s16 to s...

Page 244: ...5 is s15 s8 s9 a vector of length 4 starting at s22 is s22 s23 s16 s17 a vector of length 2 starting at d7 is d7 d4 a vector of length 3 starting at d10 is d10 d11 d8 A vector cannot contain registers from more than one bank Vector stride Vectors can occupy consecutive registers as in the examples above or they can occupy alternate registers This is controlled by the STRIDE bits in the FPSCR see F...

Page 245: ...d Fn Fm Op Fd Fm is as follows If Fd is in the first bank of registers s0 to s7 or d0 to d3 the operation is scalar If the Fm is in the first bank of registers but Fd is not the operation is mixed If neither Fd nor Fm are in the first bank of registers the operation is vector Scalar operations Op acts on the value in Fm and the value in Fn if present The result is placed in Fd Vector operations Op...

Page 246: ...AT instruction see FMRX FMXR and FMSTAT on page 6 33 Following an FCMP instruction the precise meanings of the flags are different from their meanings following an ARM data processing instruction This is because floating point values are never unsigned so the unsigned conditions are not needed Not a Number NaN values have no ordering relationship with numbers or with each other so additional condi...

Page 247: ...reater than or unordered LS Unsigned lower or same Less than or equal GE Signed greater than or equal Greater than or equal LT Signed less than Less than or unordered GT Signed greater than Greater than LE Signed less than or equal Less than or equal or unordered AL Always normally omitted Always normally omitted Table 6 2 Condition codes continued Mnemonic Meaning after ARM data processing instru...

Page 248: ...se are the VFP status flags They cannot be used to control conditional execution until they have been copied into the status flags in the CPSR see VFP and condition codes on page 6 8 bit 24 is the flush to zero mode control bit 0 flush to zero mode is disabled 1 flush to zero mode is enabled Flush to zero mode can allow greater performance depending on your hardware and software at the expense of ...

Page 249: ...nual for the VFP coprocessor you are using bits 4 0 are the cumulative exception bits IXC inexact exception UFC underflow exception OFC overflow exception DZC division by zero exception IOC invalid operation exception Cumulative exception bits are set when the corresponding exception occurs They remain set until you clear them by writing directly to the FPSCR all other bits are unused in the basic...

Page 250: ... registers but other VFP instructions are treated as undefined instructions bits 29 0 might be used by particular implementations of VFP You can use all the VFP functions described in this chapter without accessing these bits You must not alter these bits except in accordance with their use in a particular implementation see the technical reference manual for the VFP coprocessor you are using To a...

Page 251: ... of denormalized numbers the algorithms you are using do not generate frequent exceptions as a result of replacing denormalized numbers with 0 You can change between flush to zero and normal mode at any time if different parts of your code have different requirements Numbers already in registers are not affected by changing mode 6 6 2 The effects of using flush to zero mode With certain exceptions...

Page 252: ...n denormalized numbers even in flush to zero mode without flushing the results to zero Copy absolute value and negate see FABS FCPY and FNEG on page 6 16 Load and store see FLD and FST on page 6 23 Load multiple and store multiple see FLDM and FSTM on page 6 25 Transfer between floating point registers and ARM general purpose registers see FMDRR and FMRRD on page 6 29 and FMRRS and FMSRR on page 6...

Page 253: ...M on page 6 25 Floating point load multiple and store multiple FMAC FNMAC FMSC and FNMSC on page 6 27 Floating point multiply accumulate instructions FMDRR and FMRRD on page 6 29 Transfer contents between ARM registers and a double precision floating point register FMRRS and FMSRR on page 6 32 Transfer contents between a single precision floating point register and an ARM register FMRX FMXR and FM...

Page 254: ...condition codes on page 6 8 Fd is the VFP register for the result Fm is the VFP register holding the operand The precision of Fd and Fm must match the precision specified in precision Usage The FCPY instruction copies the contents ofFm into Fd The FABS instruction takes the contents of Fm clears the sign bit and places the result in Fd This gives the absolute value The FNEG instruction takes the c...

Page 256: ...l condition code see VFP and condition codes on page 6 8 Fd is the VFP register for the result Fn is the VFP register holding the first operand Fm is the VFP register holding the second operand The precision of Fd Fn and Fm must match the precision specified in precision Usage The FADD instruction adds the values in Fn and Fm and places the result in Fd The FSUB instruction subtracts the value in ...

Page 257: ... zero precision must be either S for single precision or D for double precision cond is an optional condition code see VFP and condition codes on page 6 8 Fd is the VFP register holding the first operand Fm is the VFP register holding the second operand Omit Fm for a compare with zero instruction The precision of Fd and Fm must match the precision specified in precision Usage The FCMP instruction ...

Page 258: ...d Sm where cond is an optional condition code see VFP and condition codes on page 6 8 Dd is a double precision VFP register for the result Sm is a single precision VFP register holding the operand Usage The FCVTDS instruction converts the single precision value in Sm to double precision and places the result in Dd Exceptions FCVTDS instructions can produce Invalid Operation exceptions Examples FCV...

Page 259: ...is an optional condition code see VFP and condition codes on page 6 8 Sd is a single precision VFP register for the result Dm is a double precision VFP register holding the operand Usage The FCVTSD instruction converts the double precision value in Dm to single precision and places the result in Sd Exceptions FCVTSD instructions can produce Invalid Operation Overflow Underflow or Inexact exception...

Page 260: ...ional condition code see VFP and condition codes on page 6 8 Fd is the VFP register for the result Fn is the VFP register holding the first operand Fm is the VFP register holding the second operand The precision of Fd Fn and Fm must match the precision specified in precision Usage The FDIV instruction divides the value in Fn by the value in Fm and places the result in Fd Exceptions FDIV operations...

Page 261: ... address for the transfer offset is an optional numeric expression It must evaluate to a numeric constant at assembly time The value must be a multiple of 4 and lie in the range 1020 to 1020 The value is added to the base address to form the address used for the transfer label is a program relative expression See Register relative and program relative expressions on page 3 23 for more information ...

Page 263: ... and the same as IA for saves FD meaning Full Descending stack operation This is the same as IA for loads and the same as DB for saves precision must be one of S for single precision D for double precision X for unspecified precision cond is an optional condition code see VFP and condition codes on page 6 8 Rn is the ARM register holding the base address for the transfer is optional specifies that...

Page 264: ...double precision registers However any or all of the specified double precision registers can actually contain two single precision values or integers The number of words transferred might be 2n or 2n 1 where n is the number of double precision registers in the list This is implementation dependent However if writeback is specified Rn is always adjusted by 2n 1 words You must only use unspecified ...

Page 265: ...an optional condition code see VFP and condition codes on page 6 8 Fd is the VFP register for the result Fn is the VFP register holding the first operand Fm is the VFP register holding the second operand The precision of Fd Fn and Fm must match the precision specified in precision Usage The FMAC instruction calculates Fd Fn Fm and places the result in Fd The FNMAC instruction calculates Fd Fn Fm a...

Page 267: ...and condition codes on page 6 8 Dn is the VFP double precision register Rd Rn are ARM registers Do not use r15 Usage FMDRR Dn Rd Rn transfers the contents of Rd into the low half of Dn and the contents of Rn into the high half of Dn FMRRD Rd Rn Dn transfers the contents of the low half of Dn into Rd and the contents of the high half of Dn into Rn Exceptions These instructions do not produce any ex...

Page 268: ...and condition codes on page 6 8 Dn is the VFP double precision register Rd is the ARM register Rd must not be r15 Usage These instructions are used together as matched pairs Use FMDHR with FMDLR FMDHR copy the contents of Rd into the high half of Dn FMDLR copy the contents of Rd into the low half of Dn Use FMRDH with FMRDL FMRDH copy the contents of the high half of Dn into Rd FMRDL copy the conte...

Page 269: ...Syntax FMRS cond Rd Sn FMSR cond Sn Rd where cond is an optional condition code see VFP and condition codes on page 6 8 Sn is the VFP single precision register Rd is the ARM register Rd must not be r15 Usage The FMRS instruction transfers the contents of Sn into Rd The FMSR instruction transfers the contents of Rd into Sn Exceptions These instructions do not produce any exceptions Examples FMRS r2...

Page 270: ...re two consecutive VFP single precision registers Rd Rn are the ARM registers Do not use r15 Usage The FMRRS instruction transfers the contents of Sn into Rd and the contents of Sm into Rn The FMSRR instruction transfers the contents of Rd into Sn and the contents of Rn into Sm Exceptions These instructions do not produce any exceptions Architectures These instructions are available in VFPv2 and a...

Page 271: ...CR FPSID or FPEXC see Floating point registers on page 6 5 Rd is the ARM register Usage The FMRX instruction transfers the contents of VFPsysreg into Rd The FMXR instruction transfers the contents of Rd into VFPsysreg The FMSTAT instruction is a synonym for FMRX r15 FPSCR It transfers the floating point condition flags to the corresponding flags in the ARM CPSR see VFP and condition codes on page ...

Page 272: ...ptional condition code see VFP and condition codes on page 6 8 Fd is the VFP register for the result Fn is the VFP register holding the first operand Fm is the VFP register holding the second operand The precision of Fd Fn and Fm must match the precision specified in precision Usage The FMUL instruction multiplies the values in Fn and Fm and places the result in Fd The FNMUL instruction multiplies...

Page 273: ...egister for the result The precision of Fd must match the precision specified in precision Sm is a single precision VFP register holding the integer operand Usage The FSITO instruction converts the signed integer value in Sm to floating point and places the result in Fd The FUITO instruction converts the unsigned integer value in Sm to floating point and places the result in Fd Exceptions FSITOS a...

Page 274: ...ngle precision or D for double precision cond is an optional condition code see VFP and condition codes on page 6 8 Fd is the VFP register for the result Fm is the VFP register holding the operand The precision of Fd and Fm must match the precision specified in precision Usage The FSQRT instruction calculates the square root of the value of the contents of Fm and places the result in Fd Exceptions...

Page 275: ...ion must be either S for single precision or D for double precision cond is an optional condition code see VFP and condition codes on page 6 8 Sd is a single precision VFP register for the integer result Fm is a VFP register holding the operand The precision of Fm must match the precision specified in precision Usage The FTOSI instruction converts the floating point value in Fm to a signed integer...

Page 276: ...nd fp register fp literal where precision can be S for single precision or D for double precision cond is an optional condition code fp register is the floating point register to be loaded fp literal is a single precision or double precision floating point literal see Floating point literals on page 3 22 Usage The assembler places the constant in a literal pool and generates a program relative FLD...

Page 277: ...Vector Floating point Programming ARM DUI 0068B Copyright 2000 2001 ARM Limited All rights reserved 6 39 Examples FLDD d1 3 12E106 loads 3 12E106 into d1 FLDS s31 3 12E 16 loads 3 12E 16 into s31 ...

Page 278: ...tions specify vectors of VFP registers using angle brackets sn is a single precision scalar register n sn is a single precision vector whose length and stride are given by the current vector length and stride starting at register n sn L is a single precision vector of length L stride 1 starting at register n sn L S is a single precision vector of length L stride S starting at register n dn is a do...

Page 279: ...iately after the last instruction Such a function would not be ATPCS conformant See the Using the Procedure Call Standard chapter in ADS Developer Guide for further information See also VFP directives and vector notation on page 6 40 VFPASSERT VECTOR on page 6 42 Note This directive does not generate any code It is only an assertion by the programmer The assembler produces error messages if any su...

Page 280: ...VFPASSERT VECTOR directive immediately after the instruction where the change occurs This is usually an FMXR instruction but might be a BL instruction If a function expects the VFP to be in vector mode on entry place a VFPASSERT VECTOR directive immediately before the first instruction Such a function would not be ATPCS conformant See the Using the Procedure Call Standard chapter in ADS Developer ...

Page 281: ...28 1 wrong length but not faulted unspecified FMRX r10 FPSCR BIC r10 r10 0x00370000 ORR r10 r10 0x00030000 set length 4 stride 1 FMXR FPSCR r10 VFPASSERT VECTOR 4 assert vector mode length 4 stride 1 fadds s24 4 s0 s8 4 okay fabss s24 2 s24 2 ERROR wrong length FMRX r10 FPSCR BIC r10 r10 0x00370000 ORR r10 r10 0x00130000 set length 4 stride 2 FMXR FPSCR r10 VFPASSERT VECTOR 4 2 assert vector mode ...

Page 283: ...e 7 2 Symbol definition directives on page 7 3 Data definition directives on page 7 13 Allocate memory define data structures set initial contents of memory Assembly control directives on page 7 26 Conditional assembly looping inclusions and macros Frame description directives on page 7 33 Reporting directives on page 7 44 Miscellaneous directives on page 7 49 Note None of these directives are ava...

Page 284: ... 7 36 MEXIT on page 7 29 DCD and DCDU on page 7 19 FRAME REGISTER on page 7 37 NOFP on page 7 65 DCDO on page 7 20 FRAME RESTORE on page 7 38 OPT on page 7 46 DCFD and DCFDU on page 7 21 FRAME SAVE on page 7 39 REQUIRE on page 7 65 DCFS and DCFSU on page 7 22 FRAME STATE REMEMBER on page 7 40 RLIST on page 7 8 DCI on page 7 23 FRAME STATE RESTORE on page 7 41 RN on page 7 67 DCQ and DCQU on page 7...

Page 285: ... LCLL and LCLS on page 7 6 Declare a local arithmetic logical or string variable SETA SETL and SETS on page 7 7 Set the value of an arithmetic logical or string variable RLIST on page 7 8 Define a name for a set of general purpose registers CN on page 7 9 Define a coprocessor register name CP on page 7 10 Define a coprocessor name DN and SN on page 7 11 Define a double precision or single precisio...

Page 286: ...LA GBLL or GBLS variable is the name of the variable variable must be unique amongst symbols within a source file Usage Using one of these directives for a variable that is already defined re initializes the variable to the same values given above The scope of the variable is limited to the source file that contains it Set the value of the variable with a SETA SETL or SETS directive see SETA SETL ...

Page 287: ...er in a SPACE directive Example 7 1 GBLA objectsize declare the variable name objectsize SETA 0xFF set its value other code SPACE objectsize quote the variable Example 7 2 shows how to declare and set a variable when you invoke armasm Use this when you need to set the value of a variable at assembly time pd is a synonym for predefine Example 7 2 armasm pd objectsize SETA 0xFF o objectfile sourcefi...

Page 288: ...able must be unique within the macro that contains it Usage Using one of these directives for a variable that is already defined re initializes the variable to the same values given above The scope of the variable is limited to a particular instantiation of the macro that contains it see MACRO and MEND on page 7 27 Set the value of the variable with a SETA SETL or SETS directive see SETA SETL and ...

Page 289: ...S LCLA LCLL or LCLS directive expr is an expression which is numeric for SETA see Numeric expressions on page 3 20 logical for SETL see Logical expressions on page 3 23 string for SETS see String expressions on page 3 19 Usage You must declare variable using a global or local declaration directive before using one of these directives See GBLA GBLL and GBLS on page 7 4 and LCLA LCLL and LCLS on pag...

Page 290: ... register list must be enclosed in braces Usage Use RLIST to give a name to a set of registers to be transferred by the LDM or STM instructions LDM and STM always put the lowest physical register numbers at the lowest address in memory regardless of the order they are supplied to the LDM or STM instruction If you have defined your own symbolic register names it can be less apparent that a register...

Page 291: ...ot be the same as any of the predefined names listed in Predefined register and coprocessor names on page 3 9 expr evaluates to a coprocessor register number from 0 to 15 Usage Use CN to allocate convenient names to registers to help you remember what you use each register for Note Avoid conflicting uses of the same register under different names The names c0 to c15 are predefined Example power CN...

Page 292: ...coprocessor name cannot be the same as any of the predefined names listed in Predefined register and coprocessor names on page 3 9 expr evaluates to a coprocessor number from 0 to 15 Usage Use CP to allocate convenient names to coprocessors to help you to remember what you use each one for Note Avoid conflicting uses of the same coprocessor under different names The names p0 to p15 are predefined ...

Page 293: ...he predefined names listed in Predefined register and coprocessor names on page 3 9 expr evaluates to a double precision VFP register number from 0 to 15 or a single precision VFP register number from 0 to 31 as appropriate Usage Use DN or SN to allocate convenient names to VFP registers to help you to remember what you use each one for Note Avoid conflicting uses of the same register under differ...

Page 294: ...the floating point register name cannot be the same as any of the predefined names listed in Predefined register and coprocessor names on page 3 9 expr evaluates to a floating point register number from 0 to 7 Usage Use FN to allocate convenient names to FPA floating point registers to help you to remember what you use each one for Note Avoid conflicting uses of the same register under different n...

Page 295: ...ocate words of memory and specify the initial contents as offsets from the static base register DCFD and DCFDU on page 7 21 Allocate double words of memory and specify the initial contents as double precision floating point numbers DCFS and DCFSU on page 7 22 Allocate words of memory and specify the initial contents as single precision floating point numbers DCI on page 7 23 Allocate words of memo...

Page 296: ... ARM pseudo instruction on page 4 82 and LDR Thumb pseudo instruction on page 5 41 for more information Use LTORG to ensure that a literal pool is assembled within range Large programs can require several literal pools Place LTORG directives after unconditional branches or subroutine return instructions so that the processor does not attempt to execute the constants as instructions The assembler w...

Page 297: ...ires the definition of the label during the first pass of the assembler base register specifies a register If base register is specified the address where the storage map starts is the sum of expr and the value in base register at runtime Usage Use the MAP directive in combination with the FIELD directive to describe a storage map Specify base register to define register relative labels The base r...

Page 298: ...age map is set by a MAP directive that specifies a base register the base register is implicit in all labels defined by following FIELD directives until the next MAP directive These register relative labels can be quoted in load and store instructions see MAP on page 7 15 Note You must be careful when using MAP FIELD and register relative labels See Describing data structures with MAP and FIELD di...

Page 299: ...see Numeric expressions on page 3 20 Usage You must use a DATA directive if you use SPACE to define labeled data within Thumb code See DATA on page 7 25 for more information Use the ALIGN directive to align any code following a SPACE directive See ALIGN on page 7 50 for more information See also DCB on page 7 18 DCD and DCDU on page 7 19 DCDO on page 7 20 DCW and DCWU on page 7 25 Example AREA MyD...

Page 300: ...to 255 see Numeric expressions on page 3 20 A quoted string The characters of the string are loaded into consecutive bytes of store Usage If DCB is followed by an instruction use an ALIGN directive to ensure that the instruction is aligned See ALIGN on page 7 50 for more information See also DCD and DCDU on page 7 19 DCQ and DCQU on page 7 24 DCW and DCWU on page 7 25 SPACE on page 7 17 Example Un...

Page 301: ...sion see Numeric expressions on page 3 20 a program relative expression Usage DCD inserts up to 3 bytes of padding before the first defined word if necessary to achieve 4 byte alignment Use DCDU if you do not require alignment See also DCB on page 7 18 DCW and DCWU on page 7 25 DCQ and DCQU on page 7 24 SPACE on page 7 17 Examples data1 DCD 1 5 20 Defines 3 words containing decimal values 1 5 and ...

Page 302: ...initial runtime contents of the memory as an offset from the static base register sb r9 Syntax label DCDO expr expr where expr is a register relative expression or label The base register must be sb Usage Use DCDO to allocate space in memory for static base register relative relocatable addresses Example IMPORT externsym DCDO externsym 32 bit word relocated by offset of externsym from base of SB s...

Page 303: ...fpliteral where fpliteral is a double precision floating point literal see Floating point literals on page 3 22 Usage The assembler inserts up to three bytes of padding before the first defined number if necessary to achieve 4 byte alignment Use DCFDU if you do not require alignment The word order used when converting fpliteral to internal form is controlled by the floating point architecture sele...

Page 304: ...etic operations DCDSU is the same except that the memory alignment is arbitrary Syntax label DCFS U fpliteral fpliteral where fpliteral is a single precision floating point literal see Floating point literals on page 3 22 Usage DCFS inserts up to three bytes of padding before the first defined number if necessary to achieve 4 byte alignment Use DCFSU if you do not require alignment The range for s...

Page 305: ...ee Numeric expressions on page 3 20 Usage The DCI directive is very like the DCD or DCW directives but the location is marked as code instead of data Use DCI when writing macros for new instructions not supported by the version of the assembler you are using In ARM code DCI inserts up to three bytes of padding before the first defined word if necessary to achieve 4 byte alignment In Thumb code DCI...

Page 306: ...numbers allowed is 0 to 264 1 In addition to the characters normally allowed in a numeric literal you can prefix literal with a minus sign In this case the range of numbers allowed is 263 to 1 The result of specifying n is the same as the result of specifying 264 n Usage DCQ inserts up to 3 bytes of padding before the first defined 8 byte block if necessary to achieve 4 byte alignment Use DCQU if ...

Page 307: ...r expr where expr is a numeric expression that evaluates to an integer in the range 32768 to 65535 see Numeric expressions on page 3 20 Usage DCW inserts a byte of padding before the first defined halfword if necessary to achieve 2 byte alignment Use DCWU if you do not require alignment See also DCB on page 7 18 DCD and DCDU on page 7 19 DCQ and DCQU on page 7 24 SPACE on page 7 17 Example data DC...

Page 308: ...age 7 27 MEXIT on page 7 29 IF ELSE and ENDIF on page 7 30 WHILE and WEND on page 7 32 7 4 1 Nesting directives The following structures can be nested to a total depth of 256 MACRO definitions WHILE WEND loops IF ELSE ENDIF conditional structures INCLUDE file inclusions The limit applies to all structures taken together however they are nested The limit is not 256 of each type of structure ...

Page 309: ...g this format parameter default value Double quotes must be used if there are any spaces within or at either end of the default value Usage If you start any WHILE WEND loops or IF ENDIF conditions within a macro they must be closed before the MEND directive is reached See MEXIT on page 7 29 if you need to allow an early exit from a macro for example from within a loop Within the macro body paramet...

Page 310: ... is not required in the expansion Do not use a dot between preceding text and a parameter Macros define the scope of local variables see LCLA LCLL and LCLS on page 7 6 Macros can be nested see Nesting directives on page 7 26 Examples macro definition MACRO start macro definition label xmac p1 p2 code label loop1 code code BGE label loop1 label loop2 code BL p1 BGT label loop2 code ADR p2 code MEND...

Page 311: ...e diagnose hello Prints hello at assembly time diagnose Prints default at assembly time 7 4 3 MEXIT The MEXIT directive is used to exit a macro definition before the end Usage Use MEXIT when you need an exit from within the body of a macro Any unclosed WHILE WEND loops or IF ENDIF conditions within the body of the macro are closed by the assembler before the macro is exited See also MACRO and MEND...

Page 312: ...receding condition fails is a synonym for ELSE The ENDIF directive marks the end of a sequence of instructions and or directives that you want to be conditionally assembled is a synonym for ENDIF Syntax IF logical expression ELSE ENDIF where logical expression is an expression that evaluates to either TRUE or FALSE See Relational operators on page 3 30 Usage Use IF with ENDIF and optionally with E...

Page 313: ...ON SETL TRUE test s Invoking armasm as follows leaves NEWVERSION undefined so the second set of instructions and directives are assembled armasm test s Example 7 4 assembles the first set of instructions if NEWVERSION has the value TRUE or the alternative set otherwise Example 7 4 Assembly conditional on a variable being defined IF NEWVERSION TRUE first set of instructions directives ELSE alternat...

Page 314: ... expression that can evaluate to either TRUE or FALSE see Logical expressions on page 3 23 Usage Use the WHILE directive together with the WEND directive to assemble a sequence of instructions a number of times The number of repetitions can be zero You can use IF ENDIF conditions within WHILE WEND loops WHILE WEND loops can be nested see Nesting directives on page 7 26 Example count SETA 1 you are...

Page 315: ...errors in function construction particularly when you are modifying existing code allows the assembler to alert you to errors in function construction enables backtracing of function calls during debugging allows the debugger to profile assembler functions If you require profiling of assembler functions but do not need frame description directives for other purposes you must use the FUNCTION and E...

Page 316: ...f it alters the offset of the canonical frame address from the register You must use FRAME ADDRESS immediately after the instruction which changes the calculation of the canonical frame address Note If your code uses a single instruction to save registers and alter the stack pointer you can use FRAME PUSH instead of using both FRAME ADDRESS and FRAME SAVE see FRAME PUSH on page 7 36 If your code u...

Page 317: ...n There must be at least one register in the list n is the number of bytes that the stack pointer moves Usage FRAME POP is equivalent to a FRAME ADDRESS and a FRAME RESTORE directive You can use it when a single instruction loads registers and alters the stack pointer You must use FRAME POP immediately after the instruction it refers to The assembler calculates the new offset for the canonical fra...

Page 318: ... at least one register in the list n is the number of bytes that the stack pointer moves Usage FRAME PUSH is equivalent to a FRAME ADDRESS and a FRAME SAVE directive You can use it when a single instruction saves registers and alters the stack pointer You must use FRAME PUSH immediately after the instruction it refers to The assembler calculates the new offset for the canonical frame address It as...

Page 319: ...ME SAVE r4 r6 lr 16 7 5 4 FRAME REGISTER Use the FRAME REGISTER directive to maintain a record of the locations of function arguments held in registers You can only use it within functions with FUNCTION and ENDFUNC or PROC and ENDP directives Syntax FRAME REGISTER reg1 reg2 where reg1 is the register that held the argument on entry to the function reg2 is the register in which the value is preserv...

Page 320: ... Syntax FRAME RESTORE reglist where reglist is a list of registers whose contents have been restored There must be at least one register in the list Usage Use FRAME RESTORE immediately after the callee reloads registers from the stack You need not do this after the last instruction in a function reglist can contain integer registers or floating point registers but not both Note If your code uses a...

Page 321: ... of registers stored consecutively starting at offset from the canonical frame address There must be at least one register in the list Usage Use FRAME SAVE immediately after the callee stores registers onto the stack reglist can include registers which are not required for backtracing The assembler determines which registers it needs to record in the DWARF call frame information Note If your code ...

Page 322: ...cations of saved register values can change After the exit sequence another branch can continue using the same information as before Use FRAME STATE REMEMBER to preserve this information and FRAME STATE RESTORE to restore it These directives can be nested Each FRAME STATE RESTORE directive must have a corresponding FRAME STATE REMEMBER directive See FRAME STATE RESTORE on page 7 41 FUNCTION or PRO...

Page 323: ...E STATE RESTORE directive restores information about how to calculate the canonical frame address and locations of saved register values You can only use it within functions with FUNCTION and ENDFUNC or PROC and ENDP directives Syntax FRAME STATE RESTORE Usage See FRAME STATE REMEMBER on page 7 40 FUNCTION or PROC on page 7 42 ...

Page 324: ... to identify the start of a function when producing DWARF call frame information for ELF FUNCTION sets the canonical frame address to be sp and the frame state stack to be empty Each FUNCTION directive must have a matching ENDFUNC directive You must not nest FUNCTION ENDFUNC pairs and they must not contain PROC or ENDP directives See also FRAME ADDRESS on page 7 34 to FRAME STATE RESTORE on page 7...

Page 325: ...RM DUI 0068B Copyright 2000 2001 ARM Limited All rights reserved 7 43 7 5 10 ENDFUNC or ENDP The ENDFUNC directive marks the end of an ATPCS conforming function see FUNCTION or PROC on page 7 42 ENDP is a synonym for ENDFUNC ...

Page 326: ...nsert titles and subtitles in listings 7 6 1 ASSERT The ASSERT directive generates an error message during the second pass of the assembly if a given assertion is false Syntax ASSERT logical expression where logical expression is an assertion that can evaluate to either TRUE or FALSE Usage Use ASSERT to ensure that any necessary condition is met during assembly If the assertion is false an error m...

Page 327: ...valuates to zero no action is taken during pass one string expression is printed during pass two If the expression does not evaluate to zero string expression is printed as an error message and the assembly fails string expression is an expression that evaluates to a string Usage INFO provides a flexible means for creating custom error messages See Numeric expressions on page 3 20 and String expre...

Page 328: ...w Issues an immediate form feed and starts a new page 8 Resets the line number counter to zero 16 Turns on listing for SET GBL and LCL directives 32 Turns off listing for SET GBL and LCL directives 64 Turns on listing of macro expansions 128 Turns off listing of macro expansions 256 Turns on listing of macro invocations 512 Turns off listing of macro invocations 1024 Turns on the first pass listin...

Page 329: ...ND directives The listing is produced on the second pass only Use the OPT directive to modify the default listing options from within your code See Command syntax on page 3 2 for information on the list option You can use OPT to format code listings For example you can specify a new page before functions and sections Example AREA Example CODE READONLY start code code BL func1 code OPT 4 places a p...

Page 330: ...ile If you want the title to appear on the first page the TTL directive must be on the first line of the source file Use additional TTL directives to change the title Each new TTL directive takes effect from the top of the next page Use SUBT to place a subtitle at the top of the pages of a listing file Subtitles appear in the line below the titles If you want the subtitle to appear on the first pa...

Page 331: ... AREA on page 7 52 CODE16 and CODE32 on page 7 54 END on page 7 55 ENTRY on page 7 56 EQU on page 7 57 EXPORT or GLOBAL on page 7 58 EXTERN on page 7 60 GET or INCLUDE on page 7 61 GLOBAL on page 7 62 IMPORT on page 7 62 INCBIN on page 7 63 INCLUDE on page 7 63 KEEP on page 7 64 NOFP on page 7 65 REQUIRE on page 7 65 REQUIRE8 and PRESERVE8 on page 7 66 RN on page 7 67 ROUT on page 7 68 ...

Page 332: ...Use ALIGN 4 to ensure 4 byte alignment of an address within Thumb code Use ALIGN to take advantage of caches on some ARM processors For example the ARM940T has a cache with 16 byte lines Use ALIGN 16 to align function entries on 16 byte boundaries and maximize the efficiency of the cache LDRD and STRD double word data transfers must be 8 byte aligned Use ALIGN 8 before memory allocation directives...

Page 333: ...ned only on 4 byte boundary ALIGN 8 now aligned on 8 byte boundary rout2 code AREA OffsetExample CODE DCB 1 This example places the two ALIGN 4 3 bytes in the first and fourth DCB 1 bytes of the same word AREA Example CODE READONLY start LDR r6 label1 code MOV pc lr label1 DCB 1 pc now misaligned ALIGN ensures that subroutine1 addresses subroutine1 the following instruction MOV r5 0x5 ...

Page 334: ...produced by the C compiler or for code sections otherwise associated with the C library attr are one or more comma delimited section attributes Valid attributes are ALIGN expression By default ELF sections are aligned on a 4 byte boundary expression can have any integer value from 0 to 31 The section is aligned on a 2expression byte boundary For example if expression is 10 the section is aligned o...

Page 335: ...ialized values of zero You can decide at link time whether an AREA is uninitialized or zero initialized see the Linker chapter in ADS Linker and Utilities Guide READONLY Indicates that this section should not be written to This is the default for Code areas READWRITE Indicates that this section can be read from and written to This is the default for Data areas Usage Use the AREA directive to subdi...

Page 336: ...ure of ARM and Thumb code Use CODE16 when changing from ARM state to Thumb state CODE16 must precede any Thumb code Use CODE32 when changing from Thumb state to ARM state CODE32 must precede any ARM code CODE16 and CODE32 do not assemble to instructions that change the state They only instruct the assembler to assemble Thumb or ARM instructions as appropriate and insert padding if necessary Exampl...

Page 337: ...the source file has been included in a parent file by a GET directive the assembler returns to the parent file and continues assembly at the first line following the GET directive See GET or INCLUDE on page 7 61 for more information If END is reached in the top level source file during the first pass without any errors the second pass begins If END is reached in the top level source file during th...

Page 338: ...cify at least one ENTRY point for a program If no ENTRY exists a warning is generated at link time You must not use more than one ENTRY directive in a single source file Not every source file has to have an ENTRY directive If more than one ENTRY exists in a single source file an error message is generated at assembly time Example AREA ARMex CODE READONLY ENTRY Entry point for the application ...

Page 339: ... can be any one of CODE16 CODE32 DATA You can use type only if expr is an absolute address If name is exported the name entry in the symbol table in the object file will be marked as CODE16 CODE32 or DATA according to type This can be used by the linker Usage Use EQU to define constants This is similar to the use of define to define a constant in C See KEEP on page 7 64 and EXPORT or GLOBAL on pag...

Page 340: ...ymbols are exported WEAK means that this instance of symbol should only be imported into other sources if no other source exports an alternative instance If WEAK is used without symbol all exported symbols are weak Usage Use EXPORT to give code in other files access to symbols in the current file Use the WEAK attribute to inform the linker that a different instance of symbol takes precedence over ...

Page 341: ...me a label or a constant symbol2 is the symbol name you want to appear in the object file The symbol names are case sensitive Usage Use EXPORTAS to change a symbol in the object file without having to change every instance in the source file See also EXPORT or GLOBAL on page 7 58 Examples AREA data1 DATA starts a new area data1 AREA data2 DATA starts a new area data2 EXPORTAS data2 data1 the secti...

Page 342: ...eady included Usage The name is resolved at link time to a symbol defined in a separate object file The symbol is treated as a program address If WEAK is not specified the linker generates an error if no corresponding symbol is found at link time If WEAK is specified and no corresponding symbol is found at link time If the reference is the destination of a B or BL instruction the value of the symb...

Page 343: ...t the assembler searches the current place for included files The current place is the directory where the calling file is located Use the i assembler command line option to add directories to the search path File names and directory names containing spaces must not be enclosed in double quotes The included file can contain additional GET directives to include other files see Nesting directives on...

Page 344: ... linker generating an error message if the symbol is not defined elsewhere It also prevents the linker searching libraries that are not already included Usage The name is resolved at link time to a symbol defined in a separate object file The symbol is treated as a program address If WEAK is not specified the linker generates an error if no corresponding symbol is found at link time If WEAK is spe...

Page 345: ... The contents of the file are added to the current ELF section byte for byte without being interpreted in any way Assembly continues at the line following the INCBIN directive By default the assembler searches the current place for included files The current place is the directory where the calling file is located Use the i assembler command line option to add directories to the search path File n...

Page 346: ...pecified all local symbols are kept except register relative symbols Usage By default the only symbols that the assembler describes in its output object file are exported symbols symbols that are relocated against Use KEEP to preserve local symbols that can be used to help debugging Kept symbols appear in the ARM debuggers and in linker map files KEEP cannot preserve register relative symbols see ...

Page 347: ...the NOFP directive an Unknown opcode error is generated and the assembly fails If a NOFP directive occurs after a floating point instruction the assembler generates the error Too late to ban floating point instructions and the assembly fails 7 7 17 REQUIRE The REQUIRE directive specifies a dependency between sections Syntax REQUIRE label where label is the name of the required label Usage Use REQU...

Page 348: ...RD instructions double word transfers only work correctly if the address they access is 8 byte aligned If your code includes LDRD or STRD transfers to or from the stack use REQUIRE8 to instruct the linker to ensure that your code is only called from objects that preserve 8 byte alignment of the stack If your code preserves 8 byte alignment of the stack use PRESERVE8 to inform the linker The linker...

Page 349: ... cannot be the same as any of the predefined names listed in Predefined register and coprocessor names on page 3 9 expr evaluates to a register number from 0 to 15 Usage Use RN to allocate convenient names to registers to help you to remember what you use each register for Be careful to avoid conflicting uses of the same register under different names Examples regname RN 11 defines regname for reg...

Page 350: ...he scope of local labels is the whole area if there are no ROUT directives in it see AREA on page 7 52 Use the name option to ensure that each reference is to the correct local label If the name of a label or a reference to a label does not match the preceding ROUT directive the assembler generates an error message and the assembly fails Example code routineA ROUT ROUT is not necessarily a routine...

Page 351: ...ics ARM Developer Suite A suite of applications together with supporting documentation and examples that enable you to write and debug applications for the ARM family of RISC processors ARM eXtended Debugger The ARM eXtended Debugger AXD is the latest debugger software from ARM that enables you to make use of a debug agent in order to examine and control the execution of software running on a debu...

Page 352: ... directory which contains files to be included in the compilation process Current Processor Status Register CPSR A register containing the current state of control bits and flags See also Saved Processor Status Register Debugger An application that monitors and controls the execution of a second application Usually used to find errors in the application program flow Double word A 64 bit unit of in...

Page 353: ...accessible to the subroutine that created it See also Global variables PIC Position Independent Code See also ROPI PID Position Independent Data or the ARM Platform Independent Development card See also RWPI PSR See Processor Status Register Processor Status Register A register containing various control bits and flags See also Current Processor Status Register See also Saved Processor Status Regi...

Page 354: ...lls a subroutine The stack can also be used for parameters and temporary variables SWI See Software Interrupt Target The actual target processor real or simulated on which the target application is running The fundamental object in any debugging session The basis of the debugging system The environment in which the target software will run It is essentially a collection of real or simulated proces...

Page 355: ...ary operators 3 28 block copy 2 44 Boolean constants 2 14 built in variables 3 10 case rules 2 12 character constants 2 14 code size 2 61 comments 2 13 condition code suffixes 2 21 conditional execution 2 20 constants 2 14 coprocessor names 3 9 data structures 2 51 defining macros 7 27 ELF sections 2 15 entry point 2 16 7 56 examples 2 2 2 15 2 17 2 22 2 28 2 31 2 35 2 37 2 44 2 61 2 63 examples T...

Page 356: ...ctions 2 6 Branch instructions Thumb 2 10 BX instruction 2 18 C Case rules assembly language 2 12 Characterconstants assemblylanguage 2 14 CHR operator 3 26 CN directive 7 9 Code size 2 22 2 61 CODE16 directive 2 18 3 2 7 54 CODE32 directive 2 18 7 54 Command syntax armsd 3 2 Comments assembly language 2 13 Condition code suffixes 2 21 Conditional execution assembly 2 20 2 22 Conditional execution...

Page 357: ... directive 7 16 floating point literals assembly 3 22 FN directive 7 12 FRAME ADDRESS directive 7 34 FRAME POP directive 7 35 FRAME PUSH directive 7 36 FRAME REGISTER directive 7 37 FRAME RESTORE directive 7 38 FRAME SAVE directive 7 39 FRAME STATE REMEMBER directive 7 40 FRAME STATE RESTORE directive 7 41 FUNCTION directive 7 42 G GBLA directive 3 6 3 13 7 4 7 46 GBLL directive 3 6 3 13 7 4 7 46 ...

Page 358: ...rals assembly 3 21 Numeric variable assembly 3 13 O Operator precedence assembly 3 24 3 25 Operators assembly language BASE 2 58 INDEX 2 58 AND 2 56 OPT directive 3 10 7 46 P Padding 2 56 Parameters assembly macros 2 48 pc assembly 3 10 3 15 3 23 pc assembly language 2 5 2 40 2 43 2 46 POP instruction Thumb 2 46 Processor modes 2 4 Program counter assembly 3 10 3 15 3 23 program counter assembly l...

Page 359: ...12 Symbols register based 2 58 T Thumb BX instruction 2 18 conditional execution 2 20 direct loading 2 27 example assembly language 2 18 instruction set 2 9 LDM and STM instructions 2 46 popping pc 2 43 TTL directive 7 48 U Unary operators assembly 3 26 V Variables assembly 3 13 built in 3 10 global 7 4 7 7 local 7 6 7 7 substitution 3 14 VFP directives and notation 6 40 VFPASSERT SCALAR directive...

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