Debug
ARM DDI 0363G
Copyright © 2006-2011 ARM Limited. All rights reserved.
12-22
ID073015
Non-Confidential
shows the DBGDSCCR bit assignments.
12.4.10 Instruction Transfer Register
The DBGITR enables the external debugger to feed instructions into the processor for execution
while in debug state. The DBGITR is a write-only register. Reads from the DBGITR return an
Unpredictable value.
The Instruction Transfer Register, bits [31:0] contain the ARM instruction for the processor to
execute while in debug state. The reset value of this register is Unpredictable.
Note
Writes to the DBGITR when the processor is not in debug state or the DBGDSCR[13] execute
instruction enable bit is cleared are Unpredictable. When an instruction is issued to the
processor, the debug unit prevents the next instruction from being issued until the
DBGDSCR[25] instruction complete bit is set.
12.4.11 Debug Run Control Register
The DBGDRCR Register characteristics are:
Purpose
•
Requests the processor to enter or leave debug state.
•
Clears the sticky exception bits present in the DBGDSCR.
Usage constraints
The DBGDRCR is a write-only register.
Configurations
Available in all processor configurations.
Attributes
.
shows the DBGDRCR bit assignments.
Table 12-14 DBGDSCCR Register bit assignments
Bits
Name
Reset
value
Description
[31:3]
-
0
Reserved. Do not modify on writes. On reads, the value returns zero.
[2]
nWT
0
Not write-through:
1 = normal operation of regions marked as write-back in debug state
0 = force write-through behavior for regions marked as write-back in debug state, this is
the reset value.
[1]
nIL
0
Instruction cache line-fill:
1 = normal operation of L1 instruction cache in debug state
0 = L1 instruction cache line-fills disabled in debug state, this is the reset value.
[0]
nDL
0
Data cache line-fill:
1 = normal operation of L1 data cache in debug state
0 = L1 data cache line-fills disabled in debug state, this is the reset value.