VIPER
Detailed hardware description
© 2004 Arcom Issue H
49
JTAG and debug access
Debug access to the PXA255 400MHz XScale processor is via the JTAG connector
PL10 and the reset pin of PL17. The EPI
probe has been used to debug the
PXA255 processor on the VIPER. There are many other debug tools that can be
interfaced to the VIPER for access to the JTAG Interface of the Intel XScale PXA255
processor.
The tables below detail the pins connections between the VIPER and Majic
MX
.
Compare PL10 and PL17 pin numbers to match VIPER JTAG connection to the
Majic
MX
connections
.
VIPER JTAG Connections
Connector Pin
Name
Description
1
VCC3
3.3V Supply pin to JTAG debug tool
3 GND
Ground
reference
3
GND
Not required on VIPER.
4
nTRST
PXA255 JTAG interface reset
6
TDI
JTAG test data input to the PXA255
7 TDO
JTAG test data output from the
PXA255
8
TMS
PXA255 JTAG test mode select
PL10
9
TCK
PXA255 JTAG test clock
6 RESETSW
System
reset
- - -
-
-
Not required on VIPER
PL17
-
-
Not supported by VIPER