Arcam DiVA DV88, Service Manual

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HWR- Write strobe
HRD- Read strobe
MPGCS- Chip select
MPEGIRQ-Interrupt line generated by Vaddis
Digital Video bus
The 8 bit bus YUV[0:7], with CLK27 provides the BT-656
type parallel digital video bus. The 27MHz clock is
provided on 2 different lines. CLK27 is used for the video
DAC (and also goes to the ATAPI chip). CLK27PS is used
for the progressive scan board.
Digital Audio
The audio output of the Vaddis is given out on the
following signals
SPDIF-I34
IEC 958 SPDIF output
ASDAT0 Serial data for Left and right
ASDAT1 Serial data for Lsurround,
ASDAT2 Serial data for Centre, sub
ALRCLK Wordclock
ABCLK Bit clock
Audio/Video clocks
Special note should be made of the audio and video clocks
in the system, there are separate asynchronous clocks used
for video and audio. The video runs on the system 27MHz
clock, which is generated by the Vaddis in conjunction
with the crystal Y2.
The audio clock is generated on the AV board and this is
totally asynchronous with respect to the 27MHz clock.
This is slightly unusual, since most DVD players derive
the audio clock from the video clock via a phase locked
loop
The Vaddis has a PLL which generates the audio clock,
but we don’t use it because it has horrendous jitter.
Instead, we bypass the Vaddis PLL and configure
AMCLK as an input. Our clock source is on the AV board
and this is a very low jitter oscillator.
The Vaddis maintains AV sync by dropping or repeating 1
frame of video to re-synchronise the streams when they
start to get out of sync. In practice this happens very rarely
because the 2 clocks are very accurate so the difference in
frequency will be very small. It is important to note that
without the audio clock present, no audio or video material
can be played.
CD-DSP interface
(CDERR, CDFRM, CDDAT, CDCLK.)
The Vaddis chip has a CD-DSP interface designed to
connect to DVD drives with this type of interface for CDs.
These signals are tracked on the board but they are
not
used . The data path for CDs is exactly the same as for
DVDs.
Reset and standby signals
The signal MPGRST- is an active low signal that the
micro uses to reset the Vaddis and ATAPI bridge chip.
The signal MPGSTBY- is an active low signal that the
micro uses to put the Vaddis in a low power mode while
the player is in standby.
SDRAM
The Vaddis requires some memory for video and audio
decoding and processing. This is provided by a 16MBit
synchronous DRAM (512K x 16 bit x 2 banks).
The board is arranged to allow 2 SDRAMs, but at present
we only use one. U11 is fitted while U10 is not fitted. The
Vaddis interfaces directly to the SDRAM with no other
device being involved.
PSU Synchronisation
An interesting feature of the Arcam DVD player is that the
switch mode supply on the PSU is synchronised to the
audio sampling frequency. This is done to reduce the
switch mode noise on the audio output. The PSU will free
run on its own, when tested, but when connected to the
DSP board it will lock to the audio word clock. The signal
ALRCLK is buffered by U14 to provide the signal
LRCK_PSU which goes to the PSU.
Sheet 4 - Video DAC
This sheet shows the video encoder/DAC and output
buffers.
U9 is an Analog Devices ADV7172, which does
PAL/NTSC encoding and has 6 DACs providing all our
video outputs.
It takes its input from the BT-656 video bus YUV[0..7],
this bus is clocked by CLK27 (27MHz). No H/V sync
signals are required since the H and V synchronisation is
done with embedded sync patterns in the data.
The chip has its operating parameters loaded by the system
CPU via the I2C bus.
There are 6 analogue outputs from U9. These are
composite PAL/NTSC, S-Video, and 3 lines that are
configurable (via setup menu) to be YUV or RGB. The
DACs have current outputs, so R16-21 have been chosen
to give the required output level voltage, in conjunction
with R22/24 and R23/25 which program the DAC current
outputs.
All channels are buffered by op-amps U13,16,17. These
have a gain of +2, and drive out to the AV board through a
source impedance of 75R. The AV board has filtering and
another buffer stage.
There are 2 control signals that also go to the AV board
video section.
ENABLE_AV
Used for SCART status signal. High
when player is not in standby
16/9 Used for SCART status signal. High when 16:9
TV type has been selected in setup menu.
Digital Video output
Connector CN4 provides a digital video output. This is
used in the DV27 only, for connection to the progressive
scan board.
YUV[0..7] are present on this connector along with clock
CLK27PS.
The system reset signal RESET- is provided, and the I2C
bus for control of devices on the progressive scan board.
The signal IRIRQ is connected to pick up the output of the
remote bus circuit which is on the progressive scan board.
This is an open collector signal which can be driven from
either the front panel or the remote bus input.
Sheet 5 - ATAPI Bridge and interface
U18 is a Zoran ZR36701 ATAPI to AV port bridge.
It interfaces with the system CPU via the SSC bus, made
up of the following signals:
SSC_SCLK
Clock (input to ZR36701)
SSC_MTSR Data input (CPU to ZR36701)
SSC_MRST Data output (ZR36701 to CPU)
SSC_ATN- Port ready signal (output from
ZR36701)
DRV_IRQ- Interrupt request generated by
ZR36701
The chip also receives MPGRST- to reset it from the CPU.
The system video clock CLK27 is connected to generate
timing signals.
The chip has an interface with the Vaddis referred to as the
AV interface. See the section on the Vaddis for a
description.