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MT9T111_DG - Rev. B 9/10 EN

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©2007 Aptina Imaging Corporation. All rights reserved.

MT9T111: Developer Guide

PLL and Clock Divider

Preliminary

Table 10 shows the registers related to programming the PLL and clock dividers. Refer to
the MT9T111 data sheet for more detailed descriptions of registers and variables.

Table 10:

PLL and Clock Related Registers and Variables

Map

Address

Bits

Descriptions

SYSCTL

0x0010

[13:8]

N divider value for VCO.

SYSCTL

0x0010

[7:0]

M multiplier value for VCO.

SYSCTL

0x0012

[11:8]

P3 divider for MIPI CLK.

SYSCTL

0x0012

[7:4]

P2 divider for PIXCLK.

SYSCTL

0x0012

[3:0]

P1 divider for PIXCLK.

SYSCTL

0x0014

[15]

PLL lock status. Read-only.
This bit indicates when the PLL has acquired lock. After the PLL is enabled, and the internal
counters are reset, this bit goes HIGH when PLL lock is detected.
0: PLL lock is not detected
1: PLL lock is detected

SYSCTL

0x0014

[8]

Internal PLL counter reset.
Before PLL is locked, set to “0.” After PLL is locked, reset the counters so the PLL will achieve lock
before it is used. This bit should be set to “1” after PLL is locked.

SYSCTL

0x0014

[1]

PLL enable bit. Active HIGH.
0: Disable PLL
1: Enable PLL

SYSCTL

0x0014

[0]

PLL bypass. Set to start the initialization of PLL. After PLL is locked, reset to “0” for normal
operation.
0: PLL bypass disable
1: PLL bypass enable

SYSCTL

0x0016

[9]

Enable EXTCLK input port.
0: Disable
1: Enable for normal operation

SYSCTL

0x002A

[11:8]

P6 divider for MCU CLK.

SYSCTL

0x002A

[7:4]

P5 divider for SOC CLK.

SYSCTL

0x002A

[3:0]

P4 divider for sensor CLK.

SYSCTL

0x002C

[3:0]

P7 divider for external sensor CLK.

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Summary of Contents for MT9T111

Page 1: ... s signal descriptions system connections power supply configuration and I O signal states The architecture overview describes functions of each major block and their related register descriptions inside the MT9T111 It covers the PLL the two wire serial interface the output interface GPIO signals and the OTP memory The programming and operation section provides the programming procedure and initia...

Page 2: ...these registers These are denoted below Figure 2 Firmware Variable Legend The MT9T111 was designed to facilitate customizations to optimize image quality pro cessing As the image data travels through the various stages of image processing the user can adjust the parameters in these stages to affect the images appearances This section describes most of these available adjustments Accessing the Firm...

Page 3: ...s command sequence MCU Memory R0x098E 15 0 Indirect Access Address Register R0x0990 15 0 Indirect Access Data Register Conventions and Notations This developer guide follows the conventions and notations described below Hexadecimal numbers have 0x prefix Binary numbers have 0b prefix Example 0b1010 0xA Fixed point notation 0 8 0 0 through 254 255 1 7 0 0 through 1 127 128 I O signals can be LOW 0 ...

Page 4: ...and Clocks 24 RX and TX FIFO Watermark 26 Example of ini File to Program the Watermark 27 Output Slew Rate Control 28 GPIO Control 29 Overview of GPIO Signals 29 One Time Programmable OTP Memory 33 MT9T111 Rev3 Silicon OTP Memory Programming Procedure 34 Step 1 Sensor Setup 34 Step 2 Initialize the Sensor for OTP Memory Programming 34 Step 3 Programming the Data 34 Device ID 36 Module ID 36 Master...

Page 5: ...k 59 Case 3 Parallel Output When LINE_VALID is Enabled During FRAME_VALID 59 Case 4 Parallel Output When SOI and EOI Are Enabled During FRAME_VALID 60 Case 5 Parallel Output When SOI and EOI Are Enabled But Not During FRAME_VALID 60 Case 6 Parallel Output with SOI EOI FRAME_VALID and JPEG Status Inserted 61 Case 7 Parallel Output with Embedded Thumbnail Data 61 Case 8 Parallel Output with Adaptive...

Page 6: ...ing Special Effects 90 Examples of Programming for Special Effects 90 Auto Focus 91 AF Algorithm 91 AF Mode 92 Example of Programming Simple Full Scan Triggering Operation 93 Anti Shake 94 Introduction 94 Algorithm Description 94 Configuration 95 Example of Settings for Anti Shake 95 Lens Shading Correction LC 97 Related Registers for the Lens Shading Algorithm 97 Example PGA Values for LC 97 Auto...

Page 7: ...iew 115 Register Wizard 116 Procedure for Generating Frame Timing Setting 116 Input Clock and PLL Output Frequencies 116 Image Timing 116 Register Wizard Register Output 117 Lens Calibration Procedure 122 Equipment 122 Setup 122 Calibration Procedure 123 Using DevWare for the Lens Calibration 125 Calibration Procedure Summary 128 Color Tuning Procedure 129 Calibration of True Gray TG Limits 139 Ap...

Page 8: ...g of Parallel Output When SOI and EOI Are Enabled During FRAME_VALID 60 Figure 29 Timing of Parallel Output When SOI and EOI Are Enabled But Not During FRAME_VALID 60 Figure 30 Timing of Parallel Output with SOI EOI FRAME_VALID and JPEG Status Inserted 61 Figure 31 Timing of Parallel Output with Embedded Thumbnail Data 61 Figure 32 Timing of Parallel Output with Adaptive Clock Switching 62 Figure ...

Page 9: ...PLL Menu 117 Figure 59 Lens Calibration Equipment Setup 122 Figure 60 Check Image to See if it is Flipped Correctly 124 Figure 61 Lens Regions 125 Figure 62 Sensor Array and Row Column Selection 125 Figure 63 Lens Correction Curves 126 Figure 64 Curve Percentages 127 Figure 65 Color Tuning Lab Setup 129 Figure 66 Dual Camera System Level 141 Figure 67 Dual Camera Data Flow Diagram 142 Figure 68 Du...

Page 10: ...Registers and Variables 29 Table 14 GPIO Input Output Multiplexer Control 30 Table 15 Device ID Related Registers and Variables 36 Table 16 Control of an External Secondary Sensor 37 Table 17 Transfer Modes and Sources 45 Table 18 Resolution Field 49 Table 19 JPEG Status Description 50 Table 20 Clock Switching Criteria 53 Table 21 Parallel Output Interface Options 54 Table 22 Changing Output Forma...

Page 11: ... and 1 75µm pixel technology The MT9T111 s features include 2048 x 1536 visible pixels in 1 75µm technology 30 fps maximum with 1024 x 768 YUV output 15 fps maximum with 2048 x 1536 JPEG output Parallel output MIPI transmitter MIPI receiver and two wire serial interface Dual camera support with the MT9V013 or the MT9V113 Anti Shake and auto focus features JPEG and thumbnail through parallel and MI...

Page 12: ...ore Power VDD PLL Power V DD _PLL VAA6 VAA_PIX6 Slave two wire serial interface To parallel camera port OR4 RPULL UP 5 RESET_BAR VPP7 General purpose I Os FLASH OE_BAR DOUT_LSB 1 0 GPI0 3 0 3 SADDR Standby mode EXTCLK External clock in 6 54 MHz Active LOW reset DGND DOUT 7 0 VDD CLK_P DOUT_P CLK_N To serial camera port DOUT_N VDDIO_TX2 VAA_PIX VDD_PLL VDDIO_RX V DD IO_TX 2 MIPI Power TX VDD_IO VDD...

Page 13: ... applications 4 Only one of the output modes serial or parallel can be used at any time 5 Aptina recommends a resistor value of 1 5KΩ to VDD_IO for the two wire serial interface RPULL UP how ever greater values may be used for slower transmission speed 6 VAA and VAA_PIX must be tied together 7 VPP is the one time programmable OTP memory programming voltage and should be left floating dur ing norma...

Page 14: ...s SDATA_2 I O Master two wire serial interface data to and from the MT9V013 and peripheral devices such as AF mechanics GPIO 3 0 I O General purpose digital I O could be configured for FLASH SHUTTER DOUT_LSB0 DOUT_LSB1 OE_BAR VGPIO 7 0 I O General purpose digital I O used for AF function can be left floating if not used DOUT 7 0 Output Eight bit image data output or most significant bits MSB of 10...

Page 15: ...X Supply I O power supply for the MIPI input interface 1 8V typical must be connected to VDD even if the interface is not used GNDIO_RX Supply I Ogroundsupply for the MIPI input interface must be connectedtoDGND even if the interface is not used VDD_VGPIO Supply I O power supply for VGPIO 7 0 signals can be left floating if the interface is not used GND_VGPIO Supply I O ground for VGPIO 7 0 Table ...

Page 16: ...ed If some of the features are not used in the sensor the input signals must be connected to either HIGH or LOW as shown in Table 3 Table 3 Attributes of I O and Power Supply Signals Signal Name Type Supply Reference Fail Safe I O If Unused Slew Rate Hysteresis Input Internal Pull Up Down EXTCLK Input VDD_IO DGND Yes N A N A Yes No RESET_BAR Input VDD_IO DGND Yes N A N A N A Yes PU SADDR Input VDD...

Page 17: ... A N A No VAA_PIX Supply AGND N A N A N A N A No VDD Supply DGND N A N A N A N A No VDD_IO Supply DGND N A N A N A N A No VDD_PLL Supply DGND N A N A N A N A No VPP Supply DGND N A No connection N A N A No VDDIO_TX Supply GNDIO_TX N A VDD N A N A No GNDIO_TX Supply VDDIO_TX N A DGND N A N A No VDDIO_RX Supply GNDIO_RX N A VDD N A N A No GNDIO_RX Supply VDDIO_RX N A DGND N A N A No VDD_VGPIO Supply...

Page 18: ...ystem power connections Aptina recommends the connections as shown in Table 6 If there are only four pins available for system power connections Aptina recommends the connections as shown in Table 7 Table 5 Power Supply Descriptions Voltage Name Description Voltage Ground Reference Note VDD Digital logic 1 8V DGND 1 2 VDD_IO Input output 1 8V or 2 8V GND_IO 1 2 VPP OTP memory 8 5V DGND VDD_PLL PLL...

Page 19: ...d the image flow pipeline have internal registers that can be controlled by the user In normal operation an integrated microcontroller autonomously controls most aspects of operation The processed image data is transmitted to the host system either through a parallel bus or a serial data bus through the output interface Figure 4 SOC Block Diagram Output Interface Parallel Interface MIPI Transmitte...

Page 20: ...n the PLL is enabled the MT9T111 uses the PLL output VCO clock to generate all the internal clocks All of the clocks shown in Figure 5 on page 22 are derived from the VCO see Table 10 on page 23 Table 9 on page 22 shows how to calculate the internal clock frequencies The PLL divider registers must be programmed before the PLL is enabled Aptina recom mends using the MT9T111 s Register Wizard part o...

Page 21: ...xel data DOUT 7 0 is output on the falling edge of PIXCLK PIXCLK in default mode is commonly referred to as an inverted PIXCLK because data changes on the falling edge The host controller should capture data on the rising edge of PIXCLK while LV 1 The PIXCLK polarity may be reversed by programming R0x3C20 in the TX_SS register as shown in Table 8 Table 8 Polarity of PIXCLK R0x3C20 0 Value Sensor O...

Page 22: ...U block 96 VCO P6 1 SOC CLK Internal clock for color pipe block 54 VCO P5 1 Sensor CLK Internal clock for sensor core clock 70 VCO P4 1 External sensor CLK Output clock for external sensor VCO P7 1 VCO output PLL internal clock 384 768 2 M EXTCLK N 1 f PFD PLL internal clock 2 24 EXTCLK N 1 Secondary VGA Sensor MT9V013 MCU Microcontroller RAM ROM System Interface Two wire Interface Master GPIO PLL...

Page 23: ...5 PLL lock status Read only This bit indicates when the PLL has acquired lock After the PLL is enabled and the internal counters are reset this bit goes HIGH when PLL lock is detected 0 PLL lock is not detected 1 PLL lock is detected SYSCTL 0x0014 8 Internal PLL counter reset Before PLL is locked set to 0 After PLL is locked reset the counters so the PLL will achieve lock before it is used This bi...

Page 24: ...or clock will be reduced by half Internal logic will disable the pixel clock and re program the divider value Internal delay will be applied during this change to avoid any clock glitches Example of Code to Program PLL and Clocks The following ini code example shows how to program the PLL and initialize the clocks PLL Setup 16 MHz External From Wizard Input Frequency 16 000 MHz VCO Frequency 768 0...

Page 25: ... P4 69 818 MHz SOC Clock Frequency VCO P5 51 200 MHz MCU Clock Frequency VCO P6 96 000 MHz BITFIELD 0x14 1 1 Bypass PLL BITFIELD 0X14 2 0 Power down PLL REG 0x0014 0x2145 PLL control BYPASS PLL REG 0x0010 0x0010 PLL Dividers REG 0x0012 0x0070 PLL P Dividers 1 2 3 REG 0x002A 0x77EA PLL P Dividers 4 5 6 REG 0x0014 0x2545 PLL control TEST_BYPASS on REG 0x0014 0x2547 PLL control PLL_ENABLE on REG 0x00...

Page 26: ... for different clock settings and output image sizes The MT9T111 programs the TX FIFO watermark automatically but also allows the user to program the watermark values manually To activate the manual override the user must program the TX FIFO watermark and set the manual flag as shown in Table 11 The MT9T111 does not calculate the RX FIFO watermark and always uses the user programmed value Figure 6...

Page 27: ...0 Camera2 external sensor context B RX FIFO watermark value Cam_Pri Context A 0x68AA 15 0 Camera1 internal sensor context A TX FIFO manual watermark value Cam_Pri Context A 0xE8AC 0 Camera1 internal sensor context A TX FIFO manual flag 0 Disable 1 Enable Cam_Pri Context B 0x6CAA 15 0 Camera1 internal sensor context B TX FIFO manual watermark value Cam_Pri Context B 0xECAC 0 Camera1 internal sensor...

Page 28: ...e p channel transistor Slew rate control is accomplished by an external passive resistor Figure 7 shows how slew rate is measured Figure 7 Output Slew Rate Defined Table 12 shows the related registers to program slew rate for output signals Refer to the MT9T111 data sheet for more detailed AC DC electrical specifications Table 12 Slew Rate Control Related Registers Map Address Bits Descriptions SY...

Page 29: ...input VGPIO 7 0 can be programmed as a waveform generator output to control external PWM devices Table 13 shows the related registers to program GPIO signals Refer to the MT9T111 data sheet for more detail descriptions of the registers and variables Table 13 GPIO Related Registers and Variables Map Address Bits Descriptions SYSCTL 0x001A 4 This bit controls the GPIO ports when the sensor enters st...

Page 30: ... more details Figure 8 GPIO 0 Table 14 GPIO Input Output Multiplexer Control Input Mode Output Mode Register Settings 0x0606 3 0 0x0 0x0606 3 0 0xF 0x0604 11 8 0xF 0x0606 2 1 0x0604 10 0 0x0604 6 0 0x0606 3 1 0x0604 11 0 0x0604 7 0 0x0606 1 0 11 0x0604 9 8 00 0x0604 5 4 00 0x0604 13 0 GPIO 0 0x060A 0 0x0604 0 DOUT_LSB0 GPIO 1 0x060A 1 0x0604 1 DOUT_LSB1 GPIO 2 0x060A 2 OE 0x0604 2 SHUTTER GPIO 3 0...

Page 31: ... Aptina Imaging Corporation All rights reserved MT9T111 Developer Guide GPIO Control Preliminary Figure 9 GPIO 1 Figure 10 GPIO 2 GPIO 1 0 1 0 1 0 1 SYNC SYNC 0 1 0x060A 1 0x0606 1 DOUT_LSB1 Reserved 0x0604 1 0x0604 9 0x0604 13 0x0604 5 Reserved GPIO 2 0 1 0 1 0 1 SYNC SYNC OE_BAR 0x060A 2 0x0606 2 SHUTTER Reserved 0x0604 2 0x0604 10 0x0604 6 ...

Page 32: ...Aptina Imaging Corporation All rights reserved MT9T111 Developer Guide GPIO Control Preliminary Figure 11 GPIO 3 Figure 12 VGPIO 7 0 GPIO 3 0 1 0 1 0 1 SYNC SYNC TRIGGER 0x060A 3 0x0606 3 FLASH Reserved 0x0604 3 0x0604 11 0x0604 7 VGPIO 7 0 0 1 SYNC SYNC 0 1 8 8 0x0610 7 0 0x060E 7 0 From Waveform Generator Output PWM 0x060C 7 0 VGPIO 7 0 8 8 8 ...

Page 33: ...facturing process can probe the sensor at the die or PCB level that is supply all the power rails clocks and two wire serial interface signals then this dedi cated high voltage pin does not need to be assigned to the module connector pin out However if the VPP signal needs to be bonded out as a pin on the module the trace for VPP needs to be able to carry a minimum of 4mA for programming only This...

Page 34: ... 0x73DA 4 WRITE R0x0014 0x2545 5 WRITE R0x0014 0x2547 6 WRITE R0x0014 0x3447 7 WRITE R0x0014 0x3047 8 POLL R0x0014 15 until its value 1 PLL locked 9 WRITE R0x0014 0x3046 10 WRITE R0x0016 0x0400 JPEG initialization workaround 11 WRITE R0x0030 0x0003 12 WRITE R0x0018 0x402C 13 POLL R0x0018 B14 until its value 0 14 WRITE R0x3812 11 7 0x05 Comparator is 5 15 WRITE VAR 24 R0x0037 0 0x0001 Probe the OTP...

Page 35: ...he address until all the LSC coefficients are programmed Notes 1 In the example above only three LSC coefficients DATA1 3 are programmed 2 Address 0x0 should be programmed with a dummy value An LSC coefficient DATA should not be programmed into it 3 Programming should always be done in sets of two DATA points Example In Steps 9 16 two data points DATA2 and DATA3 were programmed 4 While reading the...

Page 36: ...resistors are required to set each signal to a valid logic state External resistors should be pulled up to the VDD_IO source The MT9T111 samples GPIO 3 0 during the end of the reset cycle to ensure a valid state when VDD and VDD_IO come from the same power supply 2 The OTP memory must be programmed during the manufacturing process Rev3 sili con provides up to 5K bits of data for module ID and othe...

Page 37: ...l Secondary Sensor Map Address Bits Descriptions GPIO 0x0600 0 External secondary sensor RESET signal Active High GPIO 0x0600 1 External secondary sensor STANDBY signal Active High GPIO 0x0602 2 0 The OE signals for secondary sensor controls 001 Output enable for secondary sensor control RESET 010 Output enable for secondary sensor control STANDBY 100 Output enable for secondary sensor clock GPIO ...

Page 38: ...on options to adjust the output data and blanking timing It may be configured to have fixed timing or scene dependent variable timing Therefore the host controller must synchronize using FV and LV signals and latch output data only when FV 1 and LV 1 The MT9T111 provides two external data ports parallel and MIPI serial Only one inter face type can be programmed at a time The output data multiplexe...

Page 39: ... bypass stream 16 bit or JPEG encoded stream 8 bit as programmed by host or microcon troller JPEG encoded stream can work in continuous mode or spoof mode JPEG encoded stream working in continuous mode can only transmit on the parallel output port SOI EOI can be inserted before or after JPEG encoded stream working in continuous mode at the parallel output port Thumbnail can be enabled for the JPEG...

Page 40: ...bedded in the JPEG stream This thumbnail image is computed from the same image that is input to the JPEG compressor and is scaled to a user programmable size from 160 x 120 to 640 x 480 The thumbnail size must be configured to be smaller than the JPEG image size This image can be separated by parsing the stream for tags surrounding the embedded image Alternatively the embedded image can be extract...

Page 41: ...l clock is adjusted to lower clock rates based on the fullness of the output FIFO Figure 14 through Figure 18 on page 44 are examples of the JPEG stream through the parallel output interface Figure 14 illustrates data output when the pixel clock output is generated continuously during invalid data periods LV is of variable length based on data output rate In default mode for Rev3 silicon data tran...

Page 42: ...tatus followed by 4 bytes of length information When enabled the pixel clock output can be generated continuously during invalid data periods between FV and between LV In this streaming mode the amount of valid data within each line LV 1 is constant When adaptive clock mode is enabled the pixel clock is readjusted to lower clock rates based on the fullness of the output FIFO Below are some example...

Page 43: ...at any time Figure 17 JPEG Spoof Mode Timing with Adaptive Clock Notes 1 PIXCLK is reversed in this example with data output on the rising edge of PIXCLK and data captured by the host on the falling edge of PIXCLK JPEG Spoof Stream in MIPI Output Mode In MIPI output mode only the JPEG spoof stream can be output Similar to the parallel output interface the amount of expected pixel data is defined b...

Page 44: ...tart of Embedded Image SOEI and End of Embedded Image EOEI tags These tags are register programmable codes that enable a host to parse the thumbnail data from the compressed image stream Figure 18 JPEG Spoof Mode Timing with Thumbnail Notes 1 PIXCLK is inverted in this example 2 Thumbnail start and end codes are programmable by register setting 3 Status segment includes JPEG pointer table In addit...

Page 45: ...ed on the MIPI CCP interface This feature only applies to the parallel output port Continuous Mode The JPEG output clock can be configured to be either continuous or gated off while LV is de asserted The JPEG output clock can also be optionally gated off between frames to save power The JPEG data stream implements two markers SOI 0xFFD8 and EOI 0xFFD9 which can be optionally inserted before and af...

Page 46: ...he output buffer will not start transmitting until one line of data is ready in the FIFO The JPEG output clock can be configured to be either gated off or continuous while LV is de asserted The JPEG output clock can also be optionally gated off between frames to save power The adaptive clock switching feature is supported for the parallel output interface The PCLK changes according to the output b...

Page 47: ...nail is enabled a JPEG status segment is appended at the end of frame This segment is optional in continuous mode while it is mandatory for spoof mode The status segment is enclosed by SOSI EOSI codes as shown in Figure 19 Figure 19 Contents of Status Segment The contents of the status segment are summarized as follows SOSI start of status information which is coded as 0xFFBC Thumbnail index table...

Page 48: ...gure 20 JPEG Data Segment Structure Start of Embedded Image SOEI Thumbnail Line 0 End of Embedded Image EOEI Compressed Data 0 Start of Embedded Image SOEI Thumbnail Line 1 End of Embedded Image EOEI Compressed Data 1 Start of Embedded Image SOEI Thumbnail Line N End of Embedded Image EOEI Compressed Data N Dummy Pattern Padding Start of Status Information SOSI Status Segment End of Status Informa...

Page 49: ...olution to this unknown timing is to append the uncompressed image resolution and the thumbnail resolution in the status segment so that Devware is able to extract resolution information for every received frame The resolution field consists of two bytes of width and two bytes of height big endian of the uncompressed JPEG frame If the thumbnail is enabled the size of the thumbnail will also be ins...

Page 50: ...b_error 0 If asserted it indicates the reorder buffer error occurs in current frame 0 status 1 byte frame_rcv_done 7 Frame receive done If asserted it indicates that the current frame has been received by output buffer 0 fifo_watermark 1 0 6 5 Watermark of output buffer FIFO usage for this frame 11 Indicates highest utilization of output buffer FIFO is greater than 75 but less than 100 10 Indicate...

Page 51: ...overflow errors In continuous and spoof mode the following factors may trigger a FIFO overflow The output pixel clock slowed down by programming PCLK1 PCLK2 and PCLK3 divider registers while the JPEG data amount is large A decrease in the horizontal blanking time Thumbnail mode is enabled which consumes some time Frame Overflow Frame overflow may happen in bypass continuous and spoof mode This err...

Page 52: ... spoof height Parallel Output Interface Protocol The parallel output interface consists of the following signals FV LV DOUT 7 0 PIXCLK pads_slew_rate JPEG data or raw data are output on an 8 bit parallel data port DOUT 7 0 with the frame valid FV signal to qualify JPEG frame timing the data valid LV signal to qualify valid data and the output clock PIXCLK pads_slew_rate is used to control switchin...

Page 53: ...associated configuration registers 0x3C66 0x3C88 0x3C8A To utilize this feature PCLK1 should be configured as the slowest clock for example divider 6 PCLK2 should be the second slowest for example divider 3 and PCLK3 should be the fastest clock for example divider 1 After reset the output PCLK stays at PCLK1 It switches to PCLK2 when the FIFO reaches 50 percent full switches to PCLK3 when FIFO rea...

Page 54: ...am only applies to JPEG compressed stream Continuous 7 Spoof 3 4 5 6 N A Support Support en_ccir_code CCIR markers only apply to bypass mode Bypass 4 Support N A N A en_clk_invalid_data 0 PCLK is only enabled when data is valid 1 PCLK is a free running clock when FRAME_VALID is asserted Cont 1 2 3 4 5 6 7 8 9 N A Support N A en_clk_between_frames 0 Turn off clock during frame blanking 1 Turn on cl...

Page 55: ...111 Developer Guide Output Interface Timing Preliminary en_byte_swap When set it enables the swapping of the byte order between a pair of data bytes The user can always turn on this option if the user s microcontroller has the bandwith and capability Support Support Support Table 21 Parallel Output Interface Options continued Options Mode Description Case Bypass Mode Continuous Mode Spoof Mode ...

Page 56: ...ration register The user can also choose to insert CCIR codes The following scenarios apply to bypass streams on the parallel output interface Case 1 Parallel Bypass Output with Clock Enabled Figure 21 shows typical signal timing when the following options are applied 1 Set insert_ccir_code 0 2 Set en_clk_between_lines 1 3 Set en_clk_between_frames 1 Figure 21 Timing of Parallel Bypass Output with...

Page 57: ...2 Set en_clk_between_lines 0 3 Set en_clk_between_frames 0 Figure 23 Timing of Parallel Bypass Output with Clock Disabled Between Lines Notes 1 Default PIXCLK is used in this example Case 4 Parallel Bypass Output with Clock Disabled and CCIR Codes Inserted Figure 24 shows typical signal timing when the following options are applied 1 Set insert_ccir_code 1 2 Set en_clk_between_lines 0 3 Set en_clk...

Page 58: ... of FV on LV Appending JPEG status at the end of a data stream Insertion of thumbnail data These features can be set in the output buffer TX control register Thumbnail data will be embedded in the outgoing stream when programmed by the user The following scenarios apply to continuous streams of image data Case 1 Parallel Output with Continuous Clock Figure 25 shows typical signal timing when the f...

Page 59: ..._soi_eoi 0 2 Set en_clk_invalid_data 0 3 Set en_clk_between_frames 0 4 Set dup_fv_on_lv 0 Figure 26 Timing of Parallel Output with Gated Clock Notes 1 Default PIXCLK is used in this example Case 3 Parallel Output When LINE_VALID is Enabled During FRAME_VALID Figure 27 shows typical signal timing when the following options are applied 1 Set en_soi_eoi 0 2 Set en_clk_invalid_data 0 3 Set en_clk_betw...

Page 60: ...3 Set en_clk_invalid_data 0 4 Set en_clk_between_frames 0 Figure 28 Timing of Parallel Output When SOI and EOI Are Enabled During FRAME_VALID Notes 1 Default PIXCLK is used in this example Case 5 Parallel Output When SOI and EOI Are Enabled But Not During FRAME_VALID Figure 29 shows typical signal timing when the following options are applied 1 Set en_soi_eoi 1 2 Set soi_eoi_in_fv 0 3 Set en_clk_i...

Page 61: ...ming of Parallel Output with SOI EOI FRAME_VALID and JPEG Status Inserted Notes 1 Default PIXCLK is used in this example Case 7 Parallel Output with Embedded Thumbnail Data Thumbnail data can be embedded in the JPEG continuous stream which is delimited by the thumbnail header and footer Figure 31 shows typical signal timing when the following options are applied 1 Set en_soi_eoi 1 2 Set soi_eoi_in...

Page 62: ...aptive_clk 1 Figure 32 Timing of Parallel Output with Adaptive Clock Switching Notes 1 Default PIXCLK is used in this example Case 9 Parallel Output with Adaptive Clock Switching and Embedded Thumbnail Data Adaptive clock switching with thumbnail data is also supported for a JPEG continuous stream The switching can happen at any time during data transfer Figure 33 shows typical signal timing when ...

Page 63: ...per Guide Output Interface Timing Preliminary Case 10 Parallel Output with Gated PIXCLK Figure 34 shows typical signal timing when the following options and a gated PIXCLK are applied 1 Set en_soi_eoi 0 2 Set en_clk_invalid_data 0 3 Set en_clk_between_frames 0 4 Set en_adaptive_clk 1 Figure 34 Timing of Parallel Output with Gated PIXCLK Notes 1 Default PIXCLK is used in this example FV LV PIXCLK D...

Page 64: ...not apply to JPEG spoof mode If the valid JPEG data is less than spoof_width spoof height dummy data 0 s will be padded It is mandatory that the last ten bytes of the stream are two bytes of SOSI code four bytes of length information two bytes of status followed by two bytes of EOSI code This means that the minimum spoof_width has to be greater than ten Aptina recom mends setting the minimum value...

Page 65: ...s 0 Figure 36 Timing of PIXCLK Enabled Between Lines But Disabled Between Frames Notes 1 Default PIXCLK is used in this example Case 3 Thumbnail Stream with One Frame of Data When the thumbnail mode is enabled the thumbnail stream may be inserted at any time and span more than one line Figure 37 shows typical timing when there is enough data to fill in one line after the thumbnail data and the fol...

Page 66: ...ed 1 Set EN_CLK_BETWEEN_LINES 1 2 Set EN_CLK_BETWEEN_FRAMES 0 Figure 38 Timing of Thumbnail Stream with Less Than One Frame of Data Notes 1 Default PIXCLK is used in this example Case 5 Adaptive Clock Switching with PIXCLK Enabled Between Lines Adaptive clock switching is supported for a JPEG spoof stream The switching can happen at any time during data transfer Figure 39 shows typical timing when...

Page 67: ...o byte sequence For raw 10 bit Bayer data two lowest significant bits are output on GPIO 1 0 signals Selecting Output Data Formats Most of the variables used for context switching are located in the Cam_Pri_Context A ID 26 Cam_Pri_Context B ID 27 Cam_Sec_Context A ID 28 and Cam_Sec_Context B ID 29 variable map The MT9T111 can output several different formats YCbCr 565RGB 555RGB 444RGB and raw data...

Page 68: ...ains image size power mode and so on can be programmed manually The second option is to enable 8 2 bypass mode by using DOUT 7 0 only In this mode the data bits are sent out in two bytes DOUT 9 2 in the first byte and DOUT 1 0 with 0 s padded in the more significant bit positions for the second byte YUV Output The MT9T111 supports swapping YCrCb mode as illustrated in Table 24 Table 23 Output Form...

Page 69: ...mode is shown in Table 25 The odd and even bytes are swapped when luma and chroma swap is enabled R and B channels are bit wise swapped when chroma swap is enabled Table 25 RGB Ordering in Default Mode Mode swap disabled Byte D7 D6 D5 D4 D3 D2 D1 D0 565RGB Odd R7 R6 R5 R4 R3 G7 G6 G5 Even G4 G3 G2 B7 B6 B 5B4 B3 555RGB Odd 0 R7 R6 R5 R4 R3 G7 G6 Even G4 G3 G2 B7 B6 B5 B4 B3 444xRGB Odd R7 R6 R5 R4...

Page 70: ... in RAW Bayer format The output resolution should be configurable The 8 bit pattern will use the same data bits as the YUV output The walking 1s test pattern is output only during active lines and frames it is not output during blanking period The sequence is reset to start from 0 again after the blanking The walking 1s test pattern is only available in parallel mode and not in MIPI mode Figure 40...

Page 71: ...the walking 1s test pattern data width by programming register map TX_SS 0x3220 1 to 1 for 10 bit data output and 0 for 8 bit data output mode 3 Enable the walking 1s test pattern by setting SOC1 0x3290 5 4 to 10 4 Select the walking 1s test pattern output from the output multiplexer by program ming SOC1 0x321C 3 0 0x4 0x00 0x00 0x01 0x01 0x40 0x00 0x40 0x40 0x40 0x40 0x00 0x00 7 0 0x00 0x00 0x01 ...

Page 72: ...it pixel output data at column x row y with output window size of width m height n Last data output will be maintained during blanking time 2 Data is output from 4a Top left corner 0 0 across to m 1 0 4b Horizontal blanking 4c Next row 0 1 across to m 1 1 4d Horizontal blanking 4e Repeat rows until last valid image row n 1 4f Vertical blanking rows 3 Pbd is indeterminate data during blanking time ...

Page 73: ... Context A Control driver ID 18 offset 0x0C 1 0 Context B Control driver ID 18 offset 0x54 1 0 The bit definitions follow 0 Normal 1 Mirror horizontal 2 Flip vertical 3 Mirror and flip The example below shows how to mirror an image on the horizontal axis VAR 18 0x0C 0x146D READ MODE Register VAR8 1 0x00 0x06 Refresh Command The following commands show how to perform the same operation by using onl...

Page 74: ...4 offset 0x03 0x100 VAR 24 0x03 0x0100 To select the color bar test pattern modify driver ID 24 offset 0x25 0x06 VAR 24 0x25 0x06 The MT9T111 can generate the following test patterns VAR 24 0x25 0x00 Test pattern disable VAR 24 0x25 0x01 Solid white test pattern VAR 24 0x25 0x04 Grey test ramp VAR 24 0x25 0x06 Color bar test pattern VAR 24 0x25 0x0A Pseudo random test pattern To disable test patte...

Page 75: ...099E The host processor must write a variable address value to the address register then write variable data values to data register The XDMA block will translate both address and data to the corresponding memory locations The details of the physical interfaces are shown in Figure 43 Figure 43 Register and Variable Interfaces RAM MCU Core Registers SOC1 Registers SOC2 Registers Two wire serial int...

Page 76: ...control 9 09 0x0000 0x0037 0x400 0x2400 AE_Rule AE control 10 0A 0x0000 0x0030 0xA800 0x2800 AE_Track AE control 11 0B 0x0000 0x0049 0xAC00 0x2C00 AWB AWB control 12 0C 0x0000 0x0046 0xB000 0x3000 AF Auto Focus Auto focus control 13 0D 0x0000 0x003C 0xB400 0x3400 Anti Shake Anti shake control 14 0E 0x0000 0x0084 0xB800 0x3800 Stat Statistics 15 0F 0x0000 0x0054 0xBC00 0x3C00 Low light Gamma curve ...

Page 77: ...o lock 6 Turn off the PLL bypass mode 7 Set the output slew rate 8 Enable parallel output 9 Remove sensor from soft standby 10 Load PGA coefficients for LSC settings 11 Load CCM table values for AWB settings Example of ini File for Power On Sequence The following examples show more detail for the power on operation steps shown above Basic Initialization Reset Sensor REG 0x001A 0x0219 RESET_AND_MIS...

Page 78: ...1 Set 0x0028 0 en_vdd_dis_soft bit 0 2 Set 0x0018 0 standby_i2c bit 1 3 Read 0x0018 14 standby_done bit 1 for standby status Hard standby with shutdown can be entered using following commands 1 Set 0x0028 0 en_vdd_dis_soft bit 1 default state 2 Assert STANDBY Hard standby with memory retention can be entered using following commands 1 Set 0x0028 0 en_vdd_dis_soft bit 0 2 Assert STANDBY Table 27 St...

Page 79: ... Aptina Imaging Corporation All rights reserved MT9T111 Developer Guide Power On Operation Preliminary Exiting Standby Mode To exit the soft standby mode 1 The host system sets 0x0018 0 standby_i2c bit 0 To exit hard standby with shutdown 1 De assert STANDBY 2 The host programs the start up settings for CCM lens shading correction and so forth ...

Page 80: ...pplied in a particular order as shown in Figure 44 The timing requirements are shown in Table 28 It is advised that the user manually assert a hard reset upon power up for Rev2 Figure 44 Power Up Sequence Rev2 silicon Table 28 Power Up Signal Timing for Rev2 Silicon Parameter Symbol Min Typ Max Unit VDD to VDDIO VAA and VAA_PIX 0 500 ms VDD to VDD_PLL t 1 1 500 VDD to EXTCLK Activation t2 500 RESE...

Page 81: ...n a particular order as shown in Figure 45 The timing requirements for other signals are shown in Table 29 It is advised that the user manually assert a hard reset upon power up for Rev3 Figure 45 Power Up Sequence Rev3 silicon Table 29 Power Up Signal Timing Rev3 Silicon Parameter Symbol Min Typ Max Unit VDD to VDDIO VAA VDD_PLL and VAA_PIX 500 ms VDD to EXTCLK Activation t 1 500 RESET_BAR activa...

Page 82: ... FIFO is configured for operation but disabled and all outputs are tri stated These outputs can be enabled through the two wire serial inter face The hard reset signal sequence is shown in Figure 46 and the hard reset timing is shown in Table 30 Figure 46 Hard Reset Signal Sequence Table 30 Hard Reset Signal Timing Parameter Symbol Min Typ Max Unit RESET_BAR pulse width t 1 70 EXTCLKs Active ECXTC...

Page 83: ...or has the same affect as the hard reset and can be acti vated by writing to a register through the two wire serial interface The soft reset signal sequence is shown in Figure 47 and the soft reset timing is shown in Table 31 Figure 47 Soft Reset Signal Sequence Table 31 Soft Reset Signal Timing Parameter Symbol Min Typ Max Unit Active EXTCLK after soft reset command is asserted t1 100 EXTCLKs EXT...

Page 84: ...ve and the sensor must be started up by de asserting STANDBY Hard Standby With Memory Retention Mode Hard standby with memory retention mode without the loss of variable data can also be achieved This mode stores the variables and state of the sensor before entering standby similar to soft standby The power consumption is lower than that of soft standby as internal clocks are turned off and the tw...

Page 85: ...nished and the sensor core has been disabled The execution of standby will take place after the completion of the current line by default It is possible to synchronize the execution of standby with the end of frame through the standby_control register The soft standby signal sequence is shown in Figure 49 and the signal timing is shown in Table 33 Figure 49 Soft Standby Signal Sequence Table 32 Ha...

Page 86: ... adaptable camera however most of its settings are user programmable Context Switching and Output Configuration There are two contexts or modes available A and B Context A is known as the preview mode and has a default resolution of 1024 x 768 while context B is called the capture mode with a default resolution of 2048 x 1536 The context switching sequence is shown in Figure 50 Figure 50 State Mac...

Page 87: ...ters have been chosen to provide all foreseeable changes that a user would want to make between preview and capture modes Upon power up all non default register values desired should be uploaded including the mode variable values Hardware registers that correspond to the mode variable values do not need to be uploaded because the registers are overwritten upon initializa tion a context change prev...

Page 88: ...24 x 768 or lower resolution Notes 1 At all times the output sizes above must not exceed the input size to the scaled crop sizes 2 If the modification in scaling occurs for the current active context a refresh com mand sequence variable 0x0000 0x6 is needed to reflect the new values Otherwise a context switch to the targeted context will automatically refresh in these values Examples of ini Settin...

Page 89: ...0F0 PRI_A_IMAGE_HEIGHT VAR 23 0x18 0x0064 SYS_ZOOM_FACTOR VAR8 1 0x00 0x06 SEQ_CMD Digital Zoom Context A x1 6 VAR 23 0x3 0x20 ENABLE ZOOM VAR 26 0x00 0x0140 PRI_A_IMAGE_WIDTH VAR 26 0x02 0x00F0 PRI_A_IMAGE_HEIGHT VAR 23 0x18 0x00A0 SYS_ZOOM_FACTOR VAR8 1 0x00 0x06 SEQ_CMD Digital Zoom Context A x2 4 VAR 23 0x3 0x20 ENABLE ZOOM VAR 26 0x00 0x0140 PRI_A_IMAGE_WIDTH VAR 26 0x02 0x00F0 PRI_A_IMAGE_HE...

Page 90: ...gramming for Special Effects The following settings show how to program the MT9T111 for special effects Special Effect Black White VAR8 26 0x83 0x01 PRI_A_CONFIG_SYSCTRL_SELECT_FX VAR8 1 0x00 0x06 SEQ_CMD Special Effect Negative VAR8 26 0x83 0x03 PRI_A_CONFIG_SYSCTRL_SELECT_FX VAR8 1 0x00 0x06 SEQ_CMD Special Effect Solarize w Strength Control VAR8 26 0x83 0x04 PRI_A_CONFIG_SYSCTRL_SELECT_FX VAR8 ...

Page 91: ...e serial interface I2 C type driver or VGPIO driver to generate digital output signals needed to move different lens actuators The MT9T111 supports various types of actua tors including both micro electro mechanical systems MEMS and voice coil motor VCM types of actuators The MT9T111 does not support stepping motor type actua tors The AFM driver must correctly indicate at all times if the lens it ...

Page 92: ...ing mode The user can monitor the best position register located in the AF variable offset 0x0024 to monitor the lens position movement Manual mode AF offset 0x03 0 Full scan mode AF offset 0x03 1 Creep compensation mode AF offset 0x03 2 Hill climbing mode AF offset 0x03 3 Continuous AF mode AF offset 0x03 4 Figure 52 Full Scan Mode AF Table 34 Auto Focus ICs Supported by the MT9T111 Driver IC Int...

Page 93: ...1 and Rev2 to activate SDA pad REG 0x98E 0x4403 AFM Variable offset 0x0003 REG 0x990 0x8001 Set 15 1 and 0 1 Note 15 0 indicates loading is completed REG 0x98E 0xC421 AFM variable offset 0x0021 REG 0x990 0x18 Driver IC I2C address 0x18 REG 0x98E 0x3003 AF Variable offset 0x0003 REG 0x990 0x0002 set 1 1 to enter full scan operation REG 0x98E 0xB019 AF Variable offset 0x0019 REG 0x990 0x01 set 0 1 t...

Page 94: ...y in Figure 54 uses two successive image frames to compute a motion estimate The two frames are not output from the camera only the statistics are output The two frames are exposed at the fastest speed possible given the current total exposure and camera gain constraints The image size is constrained to be VGA or greater for this operation Figure 54 Anti Shake Algorithm The anti shake algorithm is...

Page 95: ... and 0x28 The value of the desired blur parameter pri_a_config_is_blur_input_parameter deter mines the desired blur in the captured image If the target is greater than the lowest blur achievable for the current motion this value will be used to determine the blur in the captured image This value typically ranges between 0x03 for sharp images and 0x07 for images with less noise The value for maximu...

Page 96: ...2 0x64 AS_STOP_ASVALUES_1 VAR8 13 0x0043 0x0F AS_STOP_ASVALUES_2 VAR8 13 0x0044 0x08 AS_STOP_ASVALUES_3 Anti Shake Sharper VAR 18 0x010E 0x0100 CAM1_AS_MAX_DIGITAL_GAIN_ALLOWED VAR8 13 0x003D 0x31 AS_START_ASVALUES_0 VAR8 13 0x003E 0x1B AS_START_ASVALUES_1 VAR8 13 0x003F 0x28 AS_START_ASVALUES_2 VAR8 13 0x0040 0x02 AS_START_ASVALUES_3 VAR8 13 0x0041 0xCD AS_STOP_ASVALUES_0 VAR8 13 0x0042 0x64 AS_S...

Page 97: ...can be measured by varying criteria including response flatness across the image or on specified lines through the center of the image color separation across the image or purely visual criteria Selection of calibration parameters should consider the evaluation criteria While response flat ness across the image may seem a desirable goal the actual implementation may result in over correction and e...

Page 98: ...682 0x100C P_G1_P1Q1 REG 0x3684 0x06F0 P_G1_P1Q2 REG 0x3686 0xCA0B P_G1_P1Q3 REG 0x3688 0xE491 P_G1_P1Q4 REG 0x36C0 0x19D2 P_G1_P2Q0 REG 0x36C2 0x9630 P_G1_P2Q1 REG 0x36C4 0x6010 P_G1_P2Q2 REG 0x36C6 0x9F0D P_G1_P2Q3 REG 0x36C8 0x1CD1 P_G1_P2Q4 REG 0x3700 0x554F P_G1_P3Q0 REG 0x3702 0x03D0 P_G1_P3Q1 REG 0x3704 0xA4F3 P_G1_P3Q2 REG 0x3706 0x8B91 P_G1_P3Q3 REG 0x3708 0x7035 P_G1_P3Q4 REG 0x3740 0x1C...

Page 99: ... P_G2_P0Q3 REG 0x3666 0x45F1 P_G2_P0Q4 REG 0x369E 0x72A8 P_G2_P1Q0 REG 0x36A0 0x444D P_G2_P1Q1 REG 0x36A2 0x342F P_G2_P1Q2 REG 0x36A4 0xF54E P_G2_P1Q3 REG 0x36A6 0xC7F1 P_G2_P1Q4 REG 0x36DE 0x2152 P_G2_P2Q0 REG 0x36E0 0xBD10 P_G2_P2Q1 REG 0x36E2 0x1D91 P_G2_P2Q2 REG 0x36E4 0x1350 P_G2_P2Q3 REG 0x36E6 0x88CF P_G2_P2Q4 REG 0x371E 0x42EF P_G2_P3Q0 REG 0x3720 0x46EF P_G2_P3Q1 REG 0x3722 0xEFD2 P_G2_P3...

Page 100: ...AWB algorithm Color Correction Procedure Color correction is done after the second black level block and before the aperture correction block The interpolated RGB values are transformed by the color correction matrix into color corrected R G and B values The color correction matrix is uploaded from the AWB driver into the corresponding registers in the color pipeline when AWB has settled The color...

Page 101: ...AWB The following example settings show the registers related to AWB control in the MT9T111 Enable AWB in Context A VAR 26 0x3D 0x0000 PRI_A_CONFIG_AWB_ALGO_ENTER VAR 26 0x3F 0x00FF PRI_A_CONFIG_AWB_ALGO_RUN VAR 26 0x41 0x0000 PRI_A_CONFIG_AWB_ALGO_LEAVE VAR8 1 0x00 0x06 SEQ_CMD Enable Manual WB in Context A VAR 26 0x3D 0x0000 PRI_A_CONFIG_AWB_ALGO_ENTER VAR 26 0x3F 0x00F7 PRI_A_CONFIG_AWB_ALGO_RU...

Page 102: ... Guide Auto White Balance AWB Preliminary Register D65 light CCM REG 0x3012 0x0380 8 COARSE_INTEGRATION_TIME REG 0x32C0 0x3923 1 COLOR_CORR_MATRIX_SCALE_14 REG 0x32C2 0x0724 1 COLOR_CORR_MATRIX_SCALE_11 REG 0x32C4 0xD9FC 2 COLOR_CORR_MATRIX_1_2 REG 0x32C6 0x0306 2 COLOR_CORR_MATRIX_3_4 REG 0x32C8 0x89D3 2 COLOR_CORR_MATRIX_5_6 REG 0x32CA 0x9622 2 COLOR_CORR_MATRIX_7_8 REG 0x32CC 0x2FC7 2 COLOR_COR...

Page 103: ...driver is activated during preview and video capture mode It relies on the statis tics engine that tracks speed and amplitude of the change of the overall luminance in the selected windows of the image Backlight compensation is achieved by weighting the luminance in the center of the image higher than the luminance on the periphery Other algorithm features include the rejection of fast fluctuation...

Page 104: ... AE algorithm consists of two parts a set of rules that decides what average bright ness target would be appropriate for the current scene based on statistics and a tracking algorithm that adjusts the exposure time and gain to the achieve the target brightness The tracking driver uses the luminance target computed by the rule driver This target can be read at ae_track_target The host can adjust th...

Page 105: ..._a and pri_b The AE algorithm tries to keep the gain below the programmed value in 0x002F by giv ing priority to increasing integration time first ae_track_max_fdzone_50Hz 0x0015 of pri_a and pri_b ae_track_max_fdzone_60Hz 0x0017 of pri_a and pri_b Maximum fd zone for integration time Specifies lowest frame rate fps is different between 50Hz and 60Hz flicker setting Example AE Control The followin...

Page 106: ...MA_BM VAR 18 0x012A 0x012C CAM1_LL_STOP_GAMMA_BM VAR 19 0x0126 0x0001 CAM2_LL_START_GAMMA_BM VAR 19 0x0128 0x0002 CAM2_LL_MID_GAMMA_BM VAR 19 0x012A 0x012C CAM2_LL_STOP_GAMMA_BM Enable Aperture Correction in Context A REG 0x98E 0x6867 MCU_ADDRESS REG 0x990 0x007D PRI_A_CONFIG_LL_ALGO_RUN REG 0x98E 0x8400 MCU_ADDRESS REG 0x990 0x06 SEQ_CMD Disable Aperture Correction in Context A REG 0x98E 0x6867 M...

Page 107: ... lit by 120Hz lighting the available exposure times are 8 3ms 16 67ms 25ms 33 33ms and so on the need for an exposure time less than 8 3ms under artificial light is extremely rare The camera designer must first detect whether there is a flickering light source in the scene and if so determine its flickering frequency In this case AE must limit the inte gration time to an integer multiple of the li...

Page 108: ...VAR8 18 0x44 0x5C CAM1_CTX_A_FDPERIOD_50HZ VAR8 18 0x45 0x4C CAM1_CTX_A_FDPERIOD_60HZ VAR8 18 0xA5 0x0C CAM1_FD_SEARCH_F1_50 VAR8 18 0xA6 0x0E CAM1_FD_SEARCH_F2_50 VAR8 18 0xA7 0x0F CAM1_FD_SEARCH_F1_60 VAR8 18 0xA8 0x11 CAM1_FD_SEARCH_F2_60 2 Fine tune the search window for 50Hz If the auto detection function has a high failure rate decrease the search_f1_50 value by minus 1 and increase by 1 the...

Page 109: ...PERIOD_SELECT VAR8 1 0x00 0x05 SEQ_CMD 2c Check the output image to see if flicker disappears 2d Monitor ae_track_fdperiod VAR 10 0x14 to see if it is equal to cam1_ctx_a_fdperiod_60hz VAR8 18 0x45 3 Verify the setting for auto mode 3a Connect the light source with 60Hz power supply 3b Load the following to enable auto mode VAR 26 0x11 0x0003 PRI_A_CONFIG_FD_ALGO_RUN VAR8 1 0x00 0x05 SEQ_CMD 3c Ch...

Page 110: ... contrast VAR 0x0F 0x0020 0x0032 another corre sponding to a normal lighting condition VAR 0x0F 0x0033 0x0045 and one corre sponding to a darker lighting condition that will suppress noise VAR 0x0F 0x0046 0x0058 From these three curves the MT9T111 will compute a gamma curve that is appropriate for the current brightness level At power up the MT9T111 loads these three tables with default values Pro...

Page 111: ...ght Scenes Dark Scenes In dark scenes the gamma function is composed with a noise reduction function to obtain the curve on the right The applied curve will smoothly transition between knee points as shown in Figure 56 Figure 56 Gamma Correction in Dark Scenes Contrast Enhancing Curve 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 0 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 0 NormalCurve 0 0 0 1 0 2 0 ...

Page 112: ...setting 0x3210 7 0 Example Gamma Control The following example settings show the registers related to gamma control in the MT9T111 Contrast Control VAR8 15 0x08 0x01 LL_GAMMA_SELECT select contrast gamma change to 0 for auto control VAR8 15 0x0B 0x00 LL_GAMMA_CONTRAST_CURVE_0 VAR8 15 0x0C 0x0B LL_GAMMA_CONTRAST_CURVE_1 VAR8 15 0x0D 0x1F LL_GAMMA_CONTRAST_CURVE_2 VAR8 15 0x0E 0x3C LL_GAMMA_CONTRAST...

Page 113: ...Settings VAR8 15 0x001E 0x00 LL_GAMMA_NEUTRAL_CURVE_0 VAR8 15 0x001F 0x1B LL_GAMMA_NEUTRAL_CURVE_1 VAR8 15 0x0020 0x2A LL_GAMMA_NEUTRAL_CURVE_2 VAR8 15 0x0021 0x3E LL_GAMMA_NEUTRAL_CURVE_3 VAR8 15 0x0022 0x5A LL_GAMMA_NEUTRAL_CURVE_4 VAR8 15 0x0023 0x70 LL_GAMMA_NEUTRAL_CURVE_5 VAR8 15 0x0024 0x81 LL_GAMMA_NEUTRAL_CURVE_6 VAR8 15 0x0025 0x90 LL_GAMMA_NEUTRAL_CURVE_7 VAR8 15 0x0026 0x9E LL_GAMMA_NE...

Page 114: ...rights reserved MT9T111 Developer Guide Gamma Preliminary VAR8 15 0x003C 0xC1 LL_GAMMA_NRCURVE_11 VAR8 15 0x003D 0xCB LL_GAMMA_NRCURVE_12 VAR8 15 0x003E 0xD5 LL_GAMMA_NRCURVE_13 VAR8 15 0x003F 0xDE LL_GAMMA_NRCURVE_14 VAR8 15 0x0040 0xE7 LL_GAMMA_NRCURVE_15 VAR8 15 0x0041 0xEF LL_GAMMA_NRCURVE_16 VAR8 15 0x0042 0xF7 LL_GAMMA_NRCURVE_17 VAR8 15 0x0043 0xFF LL_GAMMA_NRCURVE_18 ...

Page 115: ...ame rate output size and so forth to the Register Wizard Register Wizard generates initial power on file for pow ering up the sensor 2 Len Shading Correction LC The user can obtain the PGA coefficients for the particu lar lens DevWare provides easy lens calibration through a GUI 3 Color tuning The user can also obtain CCM color correction matrix and tune for auto white balance using DevWare The fo...

Page 116: ... mode the check box For Parallel Output Mode must be checked For a system running in MIPI mode only the checkbox For Parallel Output Mode must be unchecked The user also can input specific M and N values to make the checkbox Specify M value and Specify N value checked If user inputs incorrect values for M or N the box Target VCO fre quency MHz will become red indicating that the values must be cha...

Page 117: ...tings click the diskette icon in the tool bar Once the ini file is gener ated it may be loaded into DevWare If the checkbox Output as registers instead of variables is checked the saved ini file with register operation format is saved and can be transferred to a third party through the two wire serial bus master s command set This file was generated by MT9T111 Register Wizard Version 2 9 0 0 Build...

Page 118: ...z Fvco 576 MHz P2 8 P4 9 P5 12 P6 8 CONTEXT A PARAMETERS Requested Frames Per Second 27 500 Output Columns 1024 Output Rows 768 JPEG Unchecked Use Binning Checked X only Binning Unchecked Allow Skipping Unchecked Use Context B Line Time Unchecked Low Power Unchecked Blanking Computation HB Min then VB Max Frame Time 36 3636 msec Max Frame Clocks 2327272 7 clocks 64 MHz Pixel Clock divided by 1 Ski...

Page 119: ...8 clocks Actual Frame Clocks 6124401 clocks Row Time 58 422 usec 3739 clocks Frame time 95 693766 msec Frames per Sec 10 450 fps 50Hz Flicker Period 171 17 lines 60Hz Flicker Period 142 64 lines RX Trigger Mark 20 OB Trigger Mark 366 MT9T111 SOC3130 Register Wizard Defaults BITFIELD 0x14 1 1 Bypass PLL BITFIELD 0X14 2 0 Power down PLL REG 0x0014 0x2145 PLL control BYPASS PLL 8517 REG 0x0010 0x0012...

Page 120: ...rection A REG 0x990 0x00C0 192 REG 0x98E 0x4811 Fine IT Min A REG 0x990 0x0375 885 REG 0x98E 0x4813 Fine IT Max Margin A REG 0x990 0x025B 603 REG 0x98E 0x481D Base Frame Lines A REG 0x990 0x039F 927 REG 0x98E 0x481F Min Line Length A REG 0x990 0x05D0 1488 REG 0x98E 0x4825 Line Length A REG 0x990 0x09CE 2510 REG 0x98E 0x6C00 Output Width B REG 0x990 0x0800 2048 REG 0x98E 0x6C02 Output Height B REG ...

Page 121: ...8 40 REG 0x98E 0xC8A8 search_f2_60 REG 0x990 0x2B 43 REG 0x98E 0xC844 period_50Hz A REG 0x990 0xFF 255 REG 0x98E 0xC845 period_60Hz A REG 0x990 0xD4 212 REG 0x98E 0xC88C period_50Hz B REG 0x990 0xAB 171 REG 0x98E 0xC88D period_60Hz B REG 0x990 0x8F 143 REG 0x98E 0x4846 RX FIFO Watermark A REG 0x990 0x0014 20 REG 0x98E 0x68AA TX FIFO Watermark A REG 0x990 0x0218 536 REG 0x98E 0xE8AC TX FIFO Manual ...

Page 122: ...n front of the camera lens with the illumination source approximately 1 meter away from the glass and camera as shown in Figure 59 The light field created from the glass should be uniform and the lens should be focused to infinity and not on the glass plate It is important that the lens is focused as it will be used in a real camera module Figure 59 Lens Calibration Equipment Setup Note Place a bl...

Page 123: ...re that no clipping occurs in any region of the image 7 Calculate lens correction parameters Option 1 Calculate 2nd order polynomial for X and Y directions Translate polynomial coefficients into lens correction register values Option 2 Use DevWare tool See Calibration Procedure Summary on page 128 for more details To find the optical center of the lens To find the optimal lens correction register ...

Page 124: ...wing combinations have been captured 12a No Horizontal Flip No Vertical Flip 12b No Horizontal Flip Vertical Flip 12c Horizontal Flip Vertical Flip 12d Horizontal Flip No Vertical Flip 13 If required perform the calibration procedure for the following additional illumi nants If you are trying to use adaptive PGA these additional calibrations must be per formed Daylight D65 6500K Fluorescent 4200K ...

Page 125: ...1 Find the center of the lens by going to Sensor Control Lens Correction as shown in Figure 61 Click on Find Optical Center and watch the zones readjust on the image Figure 61 Lens Regions 2 Set the horizontal cursor to the center of the row line in the image as shown in Figure 62 In full resolution mode the center of the row line is set at 240 for MT9T111 The mouse cursor position can be read fro...

Page 126: ...rrection Curves 4 If the peak intensity of the green curve is not between 180 200 adjust the integration time in sensor core R0x3012 to meet this condition The red and blue curve should not clip intensity value should not be at or beyond 255 in this condition If the clipping occurs try using a different uniform light source or manually lower the analog gains from 0x302E Analog Blue Gain and 0x302C...

Page 127: ...ffect The user has the option to not completely calibrate the lens to obtain flat intensity curves by selecting different percentage for curvature One hundred percent corresponds to a completely flat curve Figure 64 shows the correlation between percent and curvature Figure 64 Curve Percentages 6 Push the Calibrate lens correction button the lens correction calibration will finish quickly and auto...

Page 128: ...Full resolution REG 0x001C 1281 MCU_BOOT_MODE REG 0x0010 288 PLL_DIVIDERS REG 0x0012 144 PLL_P_DIVIDERS REG 0x002A 30719 PLL_P4_P5_P6_DIVIDERS REG 0x002C 12407 PLL_P7_DIVIDER REG 0x0112 532 RX_FIFO_WATERMARK REG 0x3C5C 32 OB_TRIG_MARK REG 0x3330 256 OUTPUT_FORMAT_TEST REG 0x300C 3985 LINE_LENGTH_PCK REG 0x3C68 2056 OB_LINE_PIXEL_CNT REG 0x3C66 1544 OB_FRAME_LINE_CNT 6 Press the Options Button from...

Page 129: ... or Incandescent light at 2850 Kelvin For the procedure described in Figure 65 on page 129 the calibra tion for Daylight is shown first and then ask the user to repeat the process for incandescent light Figure 65 Color Tuning Lab Setup 2 Software setup 2a Start up DevWare and camera module Note Do not load Register Default settings upon starting the software 3 Preset and Load The following example...

Page 130: ...reliminary 4 Calibration in DevWare 4a Open the Cumulative Intensity Graph and adjust the shutter width so the Green in white patch is at 220 Since the light hits vertically from the top select the ROW line which comes across the top of the white color square Thus the maximum Green needed for White Balance is obtained The Region of White has the greatest Green Value for Red light Red component has...

Page 131: ... reserved MT9T111 Developer Guide Color Tuning Procedure Preliminary Make sure frame_length_lines coarse_integration time Adjust coarse_integration_time register values so the Maximum Green in the Intensity graph reaches 220 as shown in the graph above Adjust the coarse_integration_time register by changing the binary bits of the gain Start from left to right to approximate values ...

Page 132: ...nary 4b Adjust the Red and Blue Gain so that the curves overlap each other approximately Start by adjusting Red gain and then adjust Blue gain Start from adjusting Red gain and move to Blue gain note that Green Gain should not be adjusted it should be the default 1 000 or 0x0008 For red light start from adjusting blue gain Green gain should not be adjusted 1 000 or 0x0008 If Red is higher than Gre...

Page 133: ...the naming con vention is important The image should be named Module ID _ Light Condition and Red Gain _ Green Gain _ Blue Gain For the light condition field the user should enter D for D65 light and A for A28 light For example in the GUI below capturing an image taken by the Largan module with D65 and Red Gain 48 Green Gain 32 and Blue Gain 36 is shown The file name for above example will be Larg...

Page 134: ... background Capture this image and save it as Largan_D48_32_36_bk Note that _bk stands for background 4e Repeat steps 1 3 for incandescent light and save the color chart picture and the background picture as a different file name Note After switching to incandescent light reset the sensor and start from the default state 5 Calibration of Color Correction Matrix 5a Load the Largan_D48_32_36 bmp as ...

Page 135: ...All rights reserved MT9T111 Developer Guide Color Tuning Procedure Preliminary 5b Manipulate and adjust so that the Matrix dots are approximately located at the middle of each color square Note If the GainR is less than 1000 for Incandescent Light change the number to 1000 then go to Color Calibration and select Calibrate Make sure Daylight picture is for the Right matrix ...

Page 136: ...ghts reserved MT9T111 Developer Guide Color Tuning Procedure Preliminary 5c Save the calibrated Daylight picture as Matrix data file Select Calibrate Try to place the matrix dots at the center of the color squares These gain ratios are automatically loaded when the picture is loaded GainR 1000 Red Gain Green Gain GainG 1000 Green Gain Green Gain GainB 1000 Blue Gain Green Gain ...

Page 137: ...e setup is the same as previously described 6b Load DevWare and reset all registers this will enable AWB Color Correction AE and Gamma Correction 6c Load the Lens Correction setting then load new CCM setting 6d Go to Plug ins Color char Overlay v1 4 version may change as DevWare is updated Ensure the patches are right on top of the color bars in the image If not the user can adjust X Size and Y Si...

Page 138: ... 0x0053 under different light sources For incandescent light the current ccm position value should be close to 0 for daylight the current ccm position should be close to 127 6h Check under different light sources the values of red gain AWB variable 0x004E green gain AWB variable 0x004F and blue gain AWB variable 0x0050 The val ues should be close to 1 6i If needed repeat the color correction proce...

Page 139: ...d unit digital gain in AWB driver Turned off color correction and gamma correction on color pipeline 3 Calibration 3a Place and center the camera in the color temperature light box pointing at the Macbeth chart 3b Load DevWare and turn on D65 light source 3c Make sure sequencer variable 0x0002 0xF 3d Load Lens shading correction settings 3e Capture an image Repeat for CWF U30 and A28 There should ...

Page 140: ...squares middle 3 squares from the MacBeth color on the bottom row patch 20 21 22 from each dat file 3l With all 12 values 4 images x 3 squares considered above find the minimum and maximum values and set the max and min true gray values at the variables Minimum True gray values AWB variable 0x0063 Maximum True gray values AWB variable 0x0064 Note If the values are negative they should be set in tw...

Page 141: ...ger than 1 3Mp used for high quality still image capture and secondary high quality VGA resolution image sensor The MT9T111 image sensor has an integrated input MIPI interface to support a simpli fied system design for dual camera imaging systems as shown in Figure 66 The figure shows the interfaces between system components base band processor VGA sensor FLASH LED Auto Focus mechanism and so fort...

Page 142: ...off load all the image processing functionality as shown in Figure 67 Figure 67 Dual Camera Data Flow Diagram A typical dual camera interconnect drawing using the MT9T111 and MT9V013 is shown in Figure on page 144 Base Band Processor Output Port Serial Interface Sensor Array MUX MT9T111 SOC Image Processor MT9V013 Second Camera Sensor Array Parallel Pixel Data Path MIPI Serial Pixel Data Path Opti...

Page 143: ...L UP 5 RESET_BAR VPP7 General purpose I Os FLASH OE_BAR DOUT_LSB 1 0 GPI0 3 0 3 SADDR Standby mode EXTCLK External clock in 6 54 MHz Active LOW reset DGND DOUT 7 0 CLK_P DOUT_P CLK_N To serial camera port DOUT_N VDDIO_TX 2 MIPI Power TX V DD _IO V DD _VGPIO 9 SDATA_2 SCLK_2 GND_VGPIO 9 VGPI0 7 0 9 EXTCLK_OUT8 RESET_BAR_OUT8 STANDBY_OUT8 RX_DP8 RX_DN8 RX_CP8 RX_CN8 AF Control I Os EXTCLK SDATA SCLK...

Page 144: ...LK_P and CLK_N 3 The GPIO pads can serve multiple features that can be reconfigured The function and direction will vary by applications 4 Only one of the output modes serial or parallel can be used at any time 5 Aptina recommends a resistor value of 1 5KΩ to VDD_IO for the two wire serial interface RPULL UP how ever greater values may be used for slower transmission speed 6 VAA and VAA_PIX must b...

Page 145: ... and an FPGA to convert parallel data outputs to the USB port The headboard and the Demo2 board communicate through a two wire serial interface Both boards are powered by the USB interface Figure 69 shows the block diagram of the head board and the Demo2 board in parallel data configuration Figure 70 on page 146 shows the connection for using the MIPI receiver board between the head board and the ...

Page 146: ...ina Imaging Corporation All rights reserved MT9T111 Developer Guide Appendix B Demo Board Systems Preliminary Figure 70 Demo Board Serial Mode Parallel Output PIXCLK FV LV DOUT 7 0 Head Board Demo2 Board H e a d e r FPGA PC running DevWare USB Lens 230 RJ45 MT9T111 H e a d e r MIPI Receiver H e a d e r FPGA LDO RJ45 Serial Interface 5V Power Supply ...

Page 147: ...ation limits that are subject to change upon full characterization of production devices MT9T111 Developer Guide Revision History PDF 4749051511 Source 7788125767 Aptina reserves the right to change products or specifications without notice MT9T111_DG Rev B 9 10 EN 147 2007 Aptina Imaging Corporation All rights reserved Preliminary Revision History Rev C 9 10 Updated to non confidential Rev B 6 10...

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